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TAS5186DDV,TAS5186DDVR,TAS5186DDVRG4,TAS5186DDVG4, 规格书,Datasheet 资料

TM

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FEATURES

APPLICATIONS

DESCRIPTION

1070

G012

0.01

0.1

20

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P O – Output Power – W

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TAS5186

SLES136–MAY2005 6-Channel,210-W,Digital-Amplifier Power Stage

The TAS5186requires only simple passive demodu-

lation filters on its outputs to deliver high-quality,?Total Output Power@10%THD+N

high-efficiency audio amplification.The efficiency of –5×30W@6?+1×60W@3?the TAS5186is greater than90%when driving6-?

satellites and a3-?subwoofer speaker.

?105-dB SNR(A-Weighted)

?<0.05%THD+N@1W The TAS5186has an innovative protection system

integrated on-chip,safeguarding the device against a ?Power Stage Efficiency>90%Into

wide range of fault conditions that could damage the Recommended Loads(SE)

system.These safeguards are short-circuit protection,?Integrated Self-Protection Circuits overload protection,undervoltage protection,and

–Undervoltage overtemperature protection.The TAS5186has a new

proprietary current-limiting circuit that reduces the –Overtemperature

possibility of device shutdown during high-level music –Overload

transients.A new programmable overcurrent detector –Short Circuit allows the use of lower-cost inductors in the demodu-

lation output filter.

?Integrated Active-Bias Control to Avoid DC

Pop TOTAL HARMONIC DISTORTION+NOISE

vs

?Thermally Enhanced44-pin HTSSOP Package

OUTPUT POWER

?EMI-Compliant When Used With

Recommended System Design

?DVD Receiver

?Home Theater in a Box

The TAS5186is a high-performance,six-channel,

digital-amplifier power stage with an improved protec-

tion system.The TAS5186is capable of driving a

6-?,s ingle-ended load up to30W per each

front/satellite channel and a3-?,single-ended

subwoofer greater than60W at10%THD+N per-

formance.

A low-cost,high-fidelity audio system can be built

using a TI chipset comprising a modulator(e.g.,

TAS5086)and the TAS5186.This device does not

require power-up sequencing because of the internal

power-on reset.

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD,PurePath Digital are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Copyright?2005,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

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DDV PACKAGE (TOP VIEW)

P0016-01

TAS5186

SLES136–MAY 2005

These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The TAS5186is available in a thermally enhanced 44-pin HTSSOP PowerPAD?package.The heat slug is located on the top side of the device for convenient thermal coupling to a heatsink.

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TAS5186 SLES136–MAY2005

GENERAL INFORMATION(continued)

TERMINAL FUNCTIONS

TERMINAL

TYPE(1)DESCRIPTION

NAME NO.

AGND12P Analog ground

BST_A23P HS bootstrap supply(BST),capacitor to OUT_A required

BST_B29P HS bootstrap supply(BST),external capacitor to OUT_B required

BST_BIAS21P BIAS bootstrap supply,external capacitor to OUT_BIAS required

BST_C30P HS bootstrap supply(BST),external capacitor to OUT_C required

BST_D37P HS bootstrap supply(BST),external capacitor to OUT_D required

BST_E38P HS bootstrap supply(BST),external capacitor to OUT_E required

BST_F44P HS bootstrap supply(BST),external capacitor to OUT_F required

GND11P Chip ground

GVDD_ABC20P Gate drive voltage supply

GVDD_DEF3P Gate drive voltage supply

M110I Mode selection pin

M29I Mode selection pin

M38I Mode selection pin

OC_ADJ14O Overcurrent threshold programming pin,resistor to ground required

OTW16O Overtemperature warning open-drain output signal,active-low

OUT_A25O Output,half-bridge A,satellite

OUT_B27O Output,half-bridge B,satellite

OUT_BIAS22O BIAS half-bridge output pin

OUT_C32O Output,half-bridge C,subwoofer

OUT_D35O Output,half-bridge D,satellite

OUT_E40O Output,half-bridge E,satellite

OUT_F42O Output,half-bridge F,satellite

PGND_AB26P Power ground

PGND_C33P Power ground

PGND_D34P Power ground

PGND_EF1,41P Power ground

PVDD_A24P Power-supply input for half-bridge A

PVDD_B28P Power-supply input for half-bridge B

PVDD_C31P Power-supply input for half-bridge C

PVDD_D36P Power-supply input for half-bridge D

PVDD_E39P Power-supply input for half-bridge E

PVDD_F43P Power-supply input for half-bridge F

PWM_A19I PWM input signal for half-bridge A

PWM_B18I PWM input signal for half-bridge B

PWM_C17I PWM input signal for half-bridge C

PWM_D6I PWM input signal for half-bridge D

PWM_E5I PWM input signal for half-bridge E

PWM_F2I PWM input signal for half-bridge F

RESET7I Reset signal(active-low logic)

SD15O Shutdown open-drain output signal,active-low

VDD4P Power supply for digital voltage regulator

VREG13O Digital regulator supply filter pin,output

(1)I=input;O=output;P=power

3

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PACKAGE HEAT DISSIPATION RATINGS (1)

ABSOLUTE MAXIMUM RATINGS

TAS5186

SLES136–MAY 2005

Table 1.MODE Selection Pins

MODE PINS (1)MODE

M2M3NAME

DESCRIPTION

00 2.1mode Channels A,B,and C enabled;channels D,E,and F disabled

01 5.1mode All channels enabled

10/1

Reserved

(1)

M1must always be connected to ground.0indicates a pin connected to GND;1indicates a pin connected to VREG.

PARAMETER

TAS5186DDV

R θJC (°C/W)—1satellite (sat.)FET only 10.3R θJC (°C/W)—1subwoofer (sub.)FET only

5.2R θJC (°C/W)—1sat.half-bridge 5.2R θJC (°C/W)—1sub.half-bridge 2.6R θJC (°C/W)—5sat.half-bridges +1sub.

1.74Typical pad area (2)

34.9mm 2

(1)JC is junction-to-case,CH is case-to-heatsink.

(2)

R θCH is an important consideration.Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink.The R θCH with this condition is typically 2°C/W for this package.

over operating free-air temperature range (unless otherwise noted)(1)

TAS5186

VDD to AGND –0.3V to 13.2V GVDD_X to AGND –0.3V to 13.2V PVDD_X to PGND_X (2)–0.3V to 50V OUT_X to PGND_X (2)–0.3V to 50V BST_X to PGND_X (2)

–0.3V to 63.2V VREG to AGND –0.3V to 4.2V PGND_X to GND –0.3V to 0.3V PGND_X to AGND –0.3V to 0.3V GND to AGND

–0.3V to 0.3V PWM_X,OC_ADJ,M1,M2,M3to AGND –0.3V to 4.2V RESET,SD,OTW to AGND

–0.3V to 7V Maximum operating junction temperature range (T J )0to 125°C Storage temperature

–40°C to 125°C

Lead temperature –1,6mm (1/16inch)from case for 10seconds 260°C Minimum PWM pulse duration,low 30ns

(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)

These voltages represent the dc voltage +peak ac waveform measured at the terminal of the device in all conditions.

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S0061-01

TAS5186

SLES136–MAY 2005

TYPICAL SYSTEM DIAGRAM

5

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M1M2RESET

SD OTW

AGND OC_ADJ

VREG VDD

GVDD_DEF M3GND

PWM_F

OUT_F PGND_EF PVDD_F BST_F

PWM_E

OUT_E PGND_EF PVDD_E BST_E

PWM_D

OUT_D PGND_D PVDD_D BST_D

PWM_C

OUT_C PGND_C PVDD_C BST_C

PWM_B

OUT_B PGND_AB PVDD_B BST_B

PWM_A

OUT_A

PVDD_A BST_A

OUT_BIAS

BST_BIAS

B0034-01

GVDD_ABC TAS5186

SLES136–MAY 2005

FUNCTIONAL BLOCK DIAGRAM

6

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RECOMMENDED OPERATING CONDITIONS AUDIO SPECIFICATION

TAS5186

SLES136–MAY2005 MIN TYP MAX UNIT

PVDD_X Half-bridge supply,SE DC supply voltage at pin(s)040V

GVDD Gate drive and guard ring supply voltage DC voltage at pin(s)10.81213.2V

VDD Digital regulator supply DC supply voltage at pin10.81213.2V

Any value of R PU,EXT within

VPU Pullup voltage supply35 5.5V

recommended range

Resistive load impedance,satellite Recommended demodulation filter

R L,SAT46?channels(1)

Resistive load impedance,subwoofer Recommended demodulation filter

R L,SUB 2.253?channel

Minimum output inductance under

L output Demodulation filter inductance522μH

short-circuit condition

C output,sat Demodulation filter capacitance1μF

C output,sub Demodulation filter capacitance0.47μF

F PWM PWM frame rate192384432kHz

(1)Load impedance outside range listed might cause shutdown due to OLP,OTE,or NLP.

PVDD_X=40V,GVDD=12V,audio frequency=1kHz,AES17measurement filter,F

PWM =384kHz,case temperature=

75°C.Audio performance is recorded as a chipset,using TAS5086PWM processor with an effective modulation index limit of 97%.All performance is in accordance with the foregoing specifications and recommended operating conditions unless otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNIT

R L=6?,10%THD,clipped input signal30

R L=8?,10%THD,clipped input signal25

P O,sat Power output per satellite channel W

R L=6?,0dBFS,unclipped input signal25

R L=8?,0dBFS,unclipped input signal20

R L=3?,10%THD,clipped input signal60

R L=4?,10%THD,clipped input signal52

P O,sub Power output,subwoofer W

R L=3?,0dBFS,unclipped input signal50

R L=4?,0dBFS,unclipped input signal40

R L=6?,P O=25W0.3%

Total harmonic distortion+noise,

satellite R

L =6?,1W0.03%

THD+N

R L=3?,P O=50W0.5%

Total harmonic distortion+noise,

subwoofer R

L

=3?,1W0.03%

Output integrated noise,satellite A-weighted55

V nμV Output integrated noise,subwoofer A-weighted60

SNR System signal-to-noise ratio A-weighted105dB DNR Dynamic range(1)A-weighted,–60dBFs input signal105dB

P O=0W,all channels running5.1mode(2)8W Power dissipation due to idle losses

P idle

(IPVDDX)P

O

=0W,2.1mode4W

(1)SNR is calculated relative to0-dBFS input level.

(2)Actual system idle losses are affected by core losses of output inductors.

7

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ELECTRICAL CHARACTERISTICS

TAS5186

SLES136–MAY 2005

F PWM =384kHz,GVDD =12V,VDD =12V,T C (case temperature)=25°C,unless otherwise noted.All performance is in accordance with recommended operating conditions,unless otherwise specified.

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

VREG Voltage regulator,only used as reference node VDD =12V

3

3.3 3.6V Operating,50%duty cycle 720IVDD VDD supply current

mA Idle,reset mode 61650%duty cycle 522IGVDD_X

Gate supply current per half-bridge

mA

Idle,reset mode

13

50%duty cycle,without output filter or load,5.1180mode

IPVDD_X Half-bridge idle current

mA

50%duty cycle,without output filter or load,2.1100

mode

OUTPUT STAGE MOSFETs R DSon ,LS Sat Drain-to-source resistance,low side,satellite T J =25°C,includes metallization resistance 210m ?R DSon ,HS Sat Drain-to-source resistance,high side,satellite T J =25°C,includes metallization resistance 210m ?R Dson ,LS Sub Drain-to-source resistance,low side,subwoofer T J =25°C,includes metallization resistance 110m ?R Dson ,HS Sub Drain-to-source resistance,high side,subwoofer

T J =25°C,includes metallization resistance

110

m ?

I/O PROTECTION V UVP,G Undervoltage protection limit GVDD_X 10V V UVP,hyst (1)Undervoltage protection hysteresis 250mV OTW (1)Overtemperature warning

125°C Temperature drop needed below OTW temp.for OTW hyst (1)25°C OTW to be inactive after the OTW event OTE (1)Overtemperature error

155°C Temperature drop needed below OTE temp.for SD OTE HYST (1)25

°C to be released after the OTE event OLCP

Overload protection counter 1.25

ms Resistor programmable,high end,Overcurrent limit protection,sat.

5A Rocp =15k ?

I OC

Resistor programmable,high end,Overcurrent limit protection,sub.

8A Rocp =15k ?

I OCT Overcurrent response time 210ns Rocp OC programming resistor range Resistor tolerance =5%

15k ?

STATIC DIGITAL SPECIFICATION

V IH High-level input voltage 2

PWM_X,M1,M2,M3,RESET V V IL Low-level input voltage 0.8

I LEAK

Input leakage current

Static condition

–80

80

μA

OTW/SHUTDOWN (SD)Internal pullup resistor to DREG (3.3V)for SD and R INT_PU 26k ?

OTW

Internal pullup resistor only

3 3.3

3.6V OH High-level output voltage External pullup:

4.7-k ?resistor to 5V 4.5

5V V OL Low-level output voltage I O =4mA 0.20.4

FANOUT

Device fanout OTW,SD

No external pullup

30

Devices (1)Specified by design.

8

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TYPICAL CHARACTERISTICS,5.1MODE

T H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %

10

40

G001

0.01

0.1

20

11

10

P O

– Output Power – W

10

70

G002

0.01

0.1201

1

10

P O – Output Power – W

T H D +N

– T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %

PVDD – Supply Voltage – V 024681012141618202224262830323436P O – O u t p u t P o w e r –

W

G003

PVDD – Supply Voltage – V

510152025303540455055606570G004

P O – O u t p u t P o w e r – W

TAS5186

SLES136–MAY 2005

TOTAL HARMONIC DISTORTION +NOISE

TOTAL HARMONIC DISTORTION +NOISE

vs

vs

OUTPUT POWER

OUTPUT POWER

Figure 1.Figure 2.OUTPUT POWER

OUTPUT POWER

vs

vs

SUPPLY VOLTAGE

SUPPLY VOLTAGE

Figure 3.Figure 4.

9

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PVDD – Supply Voltage – V 0246810121416182022

242628

G005

P O – O u t p u t P o w e r – W

PVDD – Supply Voltage – V

051015202530354045

5055

G006

P O – O u t p u t P o w e r – W

20406080100120140160180200220240

S y s t e m E f f i c i e n c y – %

G007

P O – Total Output Power – W

0510152025303540

20406080100120140160180200220240

S y s t e m P o w e r L o s s – W

G008

P O – Total Output Power – W

TAS5186

SLES136–MAY 2005

TYPICAL CHARACTERISTICS,5.1MODE (continued)

OUTPUT POWER

OUTPUT POWER

vs

vs

SUPPLY VOLTAGE

SUPPLY VOLTAGE

Figure 5.

Figure 6.

SYSTEM EFFICIENCY

SYSTEM POWER LOSS

vs

vs

TOTAL OUTPUT POWER

TOTAL OUTPUT POWER

Figure 7.Figure 8.

10

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T C – Case Temperature – °C 0510********

354020

30

40

50

60

70

80

90

100110

G009

P O – O u t p u t P o w e r – W

T C – Case Temperature – °C

01020304050607080

20

30

40

50

60

70

80

90

100110

G010

P O – O u t p u t P o w e r – W

f – Frequency – kHz

?150

?140?130?120?110?100?90?80?70?60?50?40?30?20?1000

2

4

6

8

10

12

14

16

18

20

22

A m p l i t u d e – d B

G011

TAS5186

SLES136–MAY 2005

TYPICAL CHARACTERISTICS,5.1MODE (continued)

OUTPUT POWER

OUTPUT POWER

vs

vs

CASE TEMPERATURE

CASE TEMPERATURE

Figure 9.

Figure 10.

AMPLITUDE

vs

FREQUENCY

Figure 11.

11

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THEORY OF OPERATION

POWER SUPPLIES

SYSTEM POWER-UP/DOWN SEQUENCE

Powering Down

Error Reporting

TAS5186

SLES136–MAY 2005

decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin on the same side of the PCB as the TAS5186.It is recommended To facilitate system design,the TAS5186needs only to follow the PCB layout of the TAS5186reference a 12-V supply in addition to a typical 39-V design.For additional information on the rec-power-stage supply.An internal voltage regulator ommended power supply and required components,provides suitable voltage levels for the digital and see the application diagrams given in this data sheet.low-voltage analog circuitry.Additionally,all circuitry The 12-V supply should be powered from a requiring a floating voltage supply,e.g.,the high-side low-noise,low-output-impedance voltage regulator.gate drive,is accommodated by built-in bootstrap Likewise,the 39-V power-stage supply is assumed to circuitry requiring only a few external capacitors.have low output impedance and low noise.The power-supply sequence is not critical due to the In order to provide outstanding electrical and acoustic internal power-on-reset circuit.Moreover,the characteristics,the PWM signal path including gate TAS5186is fully protected against erroneous drive and output stage is designed as identical,power-stage turnon due to parasitic gate charging.independent half-bridges.For this reason,each Thus,voltage-supply ramp rates (dv/dt)are typically half-bridge has separate bootstrap pins (BST_X)and noncritical.

power-stage supply pins (PVDD_X).Furthermore,an additional pin (VDD)is provided as power supply for all common circuits.Although supplied from the same 12-V source,it is highly recommended to separate The TAS5186does not require a power-up sequence.GVDD_X and VDD on the printed-circuit board (PCB)The outputs of the H-bridge remain in a by RC filters (see application diagram for details).high-impedance state until the gate-drive supply volt-These RC filters provide the recommended age (GVDD_X)and VDD voltage are above the high-frequency isolation.Special attention should be undervoltage protection (UVP)voltage threshold (see paid to placing all decoupling capacitors as close to the Electrical Characteristics section of this data their associated pins as possible.In general,induct-sheet).Although not specifically required,it is rec-ance between the power-supply pins and decoupling ommended to hold RESET in a low state while capacitors must be avoided.(See reference board powering up the device.

documentation for additional information.)

When the TAS5186is being used with TI PWM For a properly functioning bootstrap circuit,a small modulators such as the TAS5086,no special atten-ceramic capacitor must be connected from each tion to the state of RESET is required,provided that bootstrap pin (BST_X)to the power-stage output pin the chipset is configured as recommended.(OUT_X).When the power-stage output is low,the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X)and the bootstrap pin.The TAS5186does not require a power-down se-When the power-stage output voltage is high,the quence.The device remains fully operational as long bootstrap capacitor voltage is shifted above the as the gate-drive supply (GVDD_X)voltage and VDD output voltage potential and thus provides a suitable voltage are above the undervoltage protection (UVP)voltage supply for the high-side gate driver.In an threshold level (see the Electrical Characteristics application with PWM switching frequencies in the section of this data sheet).Although not specifically range 352kHz to 384kHz,it is recommended to use required,it is a good practice to hold RESET low 33-nF ceramic capacitors,size 0603or 0805,for the during power down,thus preventing audible artifacts bootstrap capacitor.These 33-nF capacitors ensure including pops and clicks

sufficient energy storage,even during minimal PWM When the TAS5186is being used with TI PWM duty cycles,to keep the high-side power stage FET modulators such as the TAS5086,no special atten-(LDMOS)fully started during all of the remaining part tion to the state of RESET is required,provided that of the PWM cycle.In an application running at a the chipset is configured as recommended.reduced switching frequency,generally 250kHz to 192kHz,the bootstrap capacitor might need to be increased in value.Special attention should be paid to the power-stage power supply;this includes The SD and OTW pins are both active-low,component selection,PCB placement and routing.As open-drain outputs.Their function is for protec-indicated,each half-bridge has independent tion-mode signaling to a PWM controller or other power-stage supply pins (PVDD_X).For optimal elec-system-control device.

trical performance,EMI compliance,and system re-liability it is important that each PVDD_X pin is

12

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Device Protection System OVERCURRENT(OC)PROTECTION WITH

TAS5186 SLES136–MAY2005

Any fault resulting in device shutdown is signaled by two protection systems.The first protection system the SD pin going low.Likewise,OTW goes low when controls the power stage in order to prevent the the device junction temperature exceeds125°C(see output current from further increasing.I.e.,it performs the following table).a current-limiting function rather than prematurely

shutting down during combinations of high-level mu-

sic transients and extreme speaker load-impedance SD OTW DESCRIPTION drops.If the high-current situation persists,i.e.,the

power stage is being overloaded,a second protection 00Overtemperature(OTE)or overload(OLP)or

undervoltage(UVP)system triggers a latching shutdown,resulting in the

power stage being set in the high-impedance(Hi-Z) 01Overload(OLP)or undervoltage(UVP)

state.

10Overtemperature warning.Junction temperature

higher than125°C,typical For added flexibility,the OC threshold is 11Normal operation.Junction temperature lower than programmable within a limited range using a single 125°C,typical external resistor connected between the OC_ADJ pin

and AGND.

It should be noted that asserting RESET low forces

OC-Adjust Resistor Values Maximum Current Before OC the SD and OTW signals high independently of faults

(k?)Occurs(A)

being present.It is recommended to monitor the

155(sat.),8(sub.)

OTW signal using the system microcontroller and to

respond to an overtemperature warning signal by,18 4.5(sat.),7.5(sub.)

e.g.,turning down the volume to prevent further

It should be noted that a properly functioning heating of the device that would result in device

overcurrent detector assumes the presence of a shutdown(OTE).To reduce external component

properly designed demodulation filter at the count,an internal pullup resistor to3.3V is provided

power-stage output.Short-circuit protection is not on both the SD and OTW outputs.Level compliance

provided directly at the output pins of the power stage for5-V logic can be obtained by adding external

but only on the speaker terminals(after the demodu-pullup resistors to5V(see the Electrical Character-

lation filter).It is required to follow certain guidelines istics section of this data sheet for further specifi-

when selecting the OC threshold and an appropriate cations).

demodulation inductor.

?For the lowest-cost bill of materials in terms of

component selection,the OC threshold current The TAS5186contains advanced protection circuitry

should be limited,considering the power output carefully designed to facilitate system integration and

requirement and minimum load impedance. ease of use,as well as safeguarding the device from

Higher-impedance loads require a lower OC permanent failure due to a wide range of fault

threshold.

conditions such as short circuit,overload,and

?The demodulation filter inductor must retain at undervoltage.The TAS5186responds to a fault by

least5μH of inductance at twice the OC immediately setting the power stage in a

threshold setting.

high-impedance state(Hi-Z)and asserting the SD pin

low.In situations other than overload,the device Most inductors have decreasing inductance with in-automatically recovers when the fault condition has creasing temperature and increasing current been removed, e.g.,the supply voltage has(saturation).To some degree,an increase in tem-increasedor the temperature has dropped.For perature naturally occurs when operating at high highest possible reliability,recovering from an over-output currents,due to inductor core losses and the load fault requires external reset of the device no dc resistance of the inductor copper winding.A sooner than1second after the shutdown(see the thorough analysis of inductor saturation and thermal Device Reset section of this data sheet).properties is strongly recommended.

Setting the OC threshold too low might cause issues

such as lack of output power and/or unexpected CURRENT LIMITING AND OVERLOAD DE-

shutdowns due to sensitive overload detection. TECTION

In general,it is recommended to follow closely the The device has independent,fast-reacting current

external component selection and PCB layout as detectors with programmable trip threshold(OC

given in the application section.

threshold)on all high-side and low-side power-stage

FETs.See the following table for OC-adjust resistor

values.The detector outputs are closely monitored by

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Overtemperature Protection

UNDERVOLTAGE PROTECTION (UVP)AND DEVICE RESET

ACTIVE-BIAS CONTROL (ABC)

TAS5186

SLES136–MAY 2005

ABC can pre-charge the dc-blocking element in the audio path,i.e.,split-cap capacitors or series capaci-The TAS5186has a two-level temperature-protection tor,to the desired potential before switching is started system that asserts an active-low warning signal on the PWM outputs.(For recommended configur-(OTW)when the device junction temperature ex-ation,see the typical application schematic included ceeds 125°C (typical),and If the device junction in this data sheet).

temperature exceeds 155°C (typical),the device is put into thermal shutdown,resulting in all half-bridge The start-up sequence can be controlled through outputs being set in the high-impedance state (Hi-Z)sequencing the M3and RESET pins according to and SD being asserted low.

Table 2and Table 3.

Table 2.5.1Mode—All Output Channels Active

POWER-ON RESET (POR)

M3RESET OUT_BIAS OUT_A,OUT_D,

COMMENT _B,_C _E,_F The UVP and POR circuits of the TAS5186fully 0

Hi-Z

Hi-Z

Hi-Z

All outputs dis-protect the device in any power-up/down and abled,nothing is brownout situation.While powering up,the POR switching.circuit resets the overload circuit (OLP)and ensures 10Active Hi-Z Hi-Z

OUT_BIAS en-that all circuits are fully operational when the abled,all other GVDD_X and VDD supply voltages reach 10V outputs disabled (typical).Although GVDD_X and VDD are indepen-11Hi-Z Active Active

OUT_BIAS dis-dently monitored,a supply voltage drop below the abled,all other UVP threshold on any VDD or GVDD_X pin results in outputs switching

all half-bridge outputs immediately being set in the high-impedance (Hi-Z)state and SD being asserted low.The device automatically resumes operation Table 3.2.1Mode—Only Output Channels A,B,

when all supply voltages have increased above the and C Active

UVP threshold.

M3RESET OUT_BIAS OUT_A,OUT_D,

COMMENT _B,_C _E,_F 0

Hi-Z

Hi-Z

Hi-Z

All outputs dis-abled,nothing is When RESET is asserted low,the output FETs in all switching.half-bridges are forced into a high-impedance (Hi-Z)10Active Hi-Z Hi-Z

OUT_BIAS en-state.

abled,all other outputs disabled Asserting the RESET input low removes any fault information to be signaled on the SD output,i.e.,SD 01Hi-Z Active Hi-Z

OUT_BIAS dis-abled,all other is forced high.

outputs A rising-edge transition on the RESET input allows switching

the device to resume operation after an overload When the TAS5186is used with the TAS5086PWM fault.

modulator,no special attention to start-up sequencing is required,provided that the chipset is configured as recommended.

Audible pop noises are often associated with single-rail,single-ended power stages at power-up or at the start of switching.This commonly known problem has been virtually eliminated by incorpor-ating a proprietary active-bias control circuitry as part of the TAS5186feature set.By the use of only a few passive external components (typically resistors),the

14

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