LayoutGuide_DDR3

ISSI DDR3 SDRAM Layout Guild

Revision 0A. May 4, 2012.

Introduction

This is a general PCB layout guideline for ISSI DDR3 SDRAM, especially targeting for point to point application. Chipset companies may require for a special or additional guideline for DDR3. ISSI recommends following the chipset company’s rule first.

PCB Layout Guidelines

FR-4 is commonly used for the dielectric material. And its thickness and trace width and thickness should be adjusted for matching the impedance. Trace lengths are also important that should be determined through simulation for each signal group.

In general, ISSI recommends the minimum rules for trace in PCB as below for the crosstalk. These rules are based on the assumption of signal slew rate of 1V/1ns. In slower application, crosstalk issue would be less and closer spacing may be allowed.

1.Signals from the same net group should be routed on the same layer.

2.Signals from Byte group, such as DQS, DM and 8 bits of DQ, must be routed in the same layer

3.The deviation of signal propagation delay is dependent on the timing budget on the application. Following value in the

table is a good example for the beginning of design.

4.Minimum trace width is 0.13mm(5mil).

5.Intranet spacing, the distance between two adjacent traces within a net, is 0.2mm(7mil).

6.Internet spacing, the distance between the two outermost signals of different signal group is 15mil. Same rule applies

between one clock pair and another clock pair.

7.Differential clocks should be routed in parallel and keep the trace length short.

8.Differential clocks must be routed on the same layer and placed on an internal layer minimize the noise.

9.Keep some distance between CKE and CK/CK#

V REF control

Setup and hold time margin will be reduced when V REF has a noise. V REF should be designed by the user to provide optimum noise margin in the system. V REF is expected to track variations in V DDQ and the pick to pick noise should be met with specification.

1.1K?±1%/1K?±1%/ from V DDQ power panel.

2.Place a 0.1uF capacitor between V REF and V DDQ

3.Place a 0.1uF capacitor between V REF and V SSQ

4.V REF should have a minimum trace to reduce inductance.

5.V REF should have a wide trace. Min 20 mil is recommended.

6.V REF should keep a distance from other signals to reduce decoupling effect. At least, 25 mil is recommended.

EMI and termination.

The DDR3 SDRAM uses a programmable impedance output buffer. The output drive strength is calibrated during initialization. And this feature minimizes any process variation present in the driver. To calibrate output driver impedance, RZQ needs to be located between the ZQ ball and VSSQ. The value of RZQ must be 240? ±1%. RZQ can’t be shared. Each DDR3 should have its own RZQ. The drive strength setting is selected by programming the memory mode register setting defined by mode register 1 (MR1). And the default strength is RZQ/6(=40?). In layout, the impedance for all single ended data group should be close to 40? and that for differential should be close to 80?. Refer to the design guidelines of DRAM controller vendor for the detail restriction and recommendation.

DDR3 SDRAM also introduces a new feature “Dynamic ODT” and allows different ODT setting depending on the operation state. This feature increases flexibility to optimize termination values for different loading conditions. However, the result of enabling this feature can be different depending how ODT of DRAM controller behavior. User should follow DRAM controller guideline.

LAND pattern

Follow IPC-SM-782A, keep size of land pattern to be equal to 80% of the ball size of BGA.

For any questions, please contact the following individuals from ISSI’s applicatio n.

Anderson Zhang(Anderson_Zhang@https://www.sodocs.net/doc/e415596338.html,), Jiff Lee(jiff_lee@https://www.sodocs.net/doc/e415596338.html,), Jiho Kim(jhkim@https://www.sodocs.net/doc/e415596338.html,)