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LayoutGuide_DDR3

ISSI DDR3 SDRAM Layout Guild

Revision 0A. May 4, 2012.

Introduction

This is a general PCB layout guideline for ISSI DDR3 SDRAM, especially targeting for point to point application. Chipset companies may require for a special or additional guideline for DDR3. ISSI recommends following the chipset company’s rule first.

PCB Layout Guidelines

FR-4 is commonly used for the dielectric material. And its thickness and trace width and thickness should be adjusted for matching the impedance. Trace lengths are also important that should be determined through simulation for each signal group.

In general, ISSI recommends the minimum rules for trace in PCB as below for the crosstalk. These rules are based on the assumption of signal slew rate of 1V/1ns. In slower application, crosstalk issue would be less and closer spacing may be allowed.

1. Signals from the same net group should be routed on the same layer.

2. Signals from Byte group, such as DQS, DM and 8 bits of DQ, must be routed in the same layer

3. The deviation of signal propagation delay is dependent on the timing budget on the application. Following value in the

table is a good example for the beginning of design.

LayoutGuide_DDR3

4. Minimum trace width is 0.13mm(5mil).

5. Intranet spacing, the distance between two adjacent traces within a net, is 0.2mm(7mil).

6. Internet spacing, the distance between the two outermost signals of different signal group is 15mil. Same rule applies

between one clock pair and another clock pair.

7. Differential clocks should be routed in parallel and keep the trace length short.

8. Differential clocks must be routed on the same layer and placed on an internal layer minimize the noise.

9. Keep some distance between CKE and CK/CK#

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