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FPGA可编程逻辑器件芯片XC2V8000-4CS144I中文规格书

Configuration Data File Formats

Configuration Data File Formats

Xilinx design tools can generate configuration data files in a number of different formats, as described in Table 5-4. BitGen converts the post-PAR NCD file into a configuration file or a bitstream. PROMGen, the PROM file generator, converts one or more bitstream files into a PROM file. PROM files can be generated in a number of different file formats and does not need to be used with a PROM. They can be stored anywhere and delivered by any means.

Bitstream Overview

The Spartan-6 FPGA bitstream contains commands to the FPGA configuration logic as well as configuration data. Table 5-5 gives a typical default bitstream length for each of the Spartan-6 devices. Compression can provide a smaller bitstream.Table 5-4:

Configuration File Formats

File

Extension

Bit Swapping (1)

Xilinx Software

Tool (2)

Description

BIT

Not Bit Swapped BitGen (generated by default)Binary configuration data file containing header information

that does not need to be downloaded to the FPGA. Used to

program devices from iMPACT software with a programming

cable. RBT

Not Bit Swapped BitGen (generated if -b option is set)ASCII equivalent of the BIT file containing a text header and ASCII 1s and 0s. (Eight bits per configuration bit.)BIN

Not Bit Swapped

BitGen (generated if -g Binary:yes option is set) or PROMGen Binary configuration data file with no header information. Similar to BIT file. Can be used for custom configuration solutions (for example, microprocessors), or in some cases to program third-party devices.

MCS EXO Bit Swapped PROMGen or iMPACT software ASCII PROM file formats containing address and checksum information in addition to configuration data. Used mainly for device programmers and iMPACT software.

HEX Determined by User

PROMGen or iMPACT software ASCII PROM file format containing only configuration data. Used mainly in custom configuration solutions.

CFI

N/A

PROMGen or iMPACT software

Data file used by iMPACT software to determine PROM

options to set such as x2 and x4 data width or version control.

Notes:

1.Bit swapping is discussed in the Bit Swapping section.

2.For complete BitGen and PROMGen syntax, refer to UG628, Command Line Tools User Guide .

Table 5-5:Spartan-6 FPGA Bitstream Length

Device Total Number of Configuration Bits (1)

6SLX42,731,4886SLX92,742,5286SLX163,731,2646SLX256,440,4326SLX25T

6,440,432

The user must change the SelectMAP interface from write to read control between steps 10 and 11, and back to write control after step 11, as illustrated in Figure 6-2. The SelectMAP 16-bit data ordering applies to the ICAP interface as shown in Table 2-4, page 39 and Table 2-5, page 40.

To read registers other than STAT, the address specified in the Type-1 packet header in step 2 of Table 6-1 should be modified and the word count changed if necessary. Reading from the FDRO register is a special case that is described in Configuration Memory Read Procedure (SelectMAP).

Configuration Memory Read Procedure (SelectMAP)

The process for reading configuration memory from the FDRO register is similar to the process for reading from other registers. Additional steps are needed to accommodate the configuration logic. Configuration data coming from the FDRO register passes through the frame buffer. The first frame of readback data should be discarded. After changing the FAR or beginning to read a different frame type, it is necessary to send the DESYNC command and a new synchronization word prior to starting another read operation.1.Write the dummy and synchronization words to the device.2.Write one NOOP command.

3.Write the Shutdown command, and write NOOP commands.

4.Write the RCRC command, and write one NOOP command.

5.Write the AGHIGH command to disable the interconnect, and write one NOOP command.

6.Set the frame length register.

7.Write the Starting Frame Address to the FAR (typically 0x00000000).8.Write the RCFG command to the CMD register.

9.

Write the read FDRO register packet header to the device. The FDRO read length is given by:

FDRO Read Length = (words per frame) x (frames to read + 1) + 1

One extra frame is read to account for the frame buffer. Users should strobe readback data while DOUT_BUSY is Low. The frame buffer produces one dummy frame at the beginning of the read. Also, one extra word is read in SelectMap8 mode.10.Write to the device to flush the packet buffer.

Figure 6-2:

8-Bit SelectMAP Status Register Read

Chapter 8:Readback CRC

SelectMAP ABORT

ABORT Status Word

During the configuration ABORT sequence, the device drives a status word onto the D[7:0] pins. The status bits do not bit swap. The other data pins are always High. The key for that status word is given in Table 9-2. The ABORT sequence lasts four CCLK cycles. During those cycles, the status word changes to reflect data alignment and ABORT status. A typical sequence might be:

11011111=>DALIGN = 1,IN_ABORT_B = 1 11001111=>DALIGN = 1,IN_ABORT_B = 0 10001111=>DALIGN = 0,IN_ABORT_B = 0 10011111

=>

DALIGN = 0,

IN_ABORT_B = 1

After the last cycle, the synchronization word can be reloaded to establish data alignment.

Resuming Configuration or Readback After an Abort

There are two ways to resume configuration or readback after an ABORT: ?The device can be resynchronized after the ABORT completes.?

The device can be reset by pulsing PROGRAM_B Low at any time.

To resynchronize the device, CSI_B must be deasserted then reasserted. Configuration or readback can be resumed by sending the last configuration or readback packet that was in progress when the ABORT occurred. Alternatively, configuration or readback can be restarted from the beginning.

Table 9-2:ABORT Status Word

Bit Number

Status Bit Name Meaning

D7

CFGERR_B

Configuration error (active Low)

0 = A configuration error has occurred.1 = No configuration error.D6

DALIGN

Sync word received (active High)

0 = No sync word received.

1 = Sync word received by interface logic.D5

RIP

Readback in progress (active High)

0 = No readback in progress.1 = A readback is in progress.D4IN_ABORT_B

ABORT in progress (active Low)

0 = Abort is in progress.1 = No abort in progress.D3-D0

1111

Fixed to ones.

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