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AML8726-MX LVDS Display User Guide 20120411

AML8726-MX LVDS Display User Guide 20120411
AML8726-MX LVDS Display User Guide 20120411

Application Notes

AML8726-MX

LVDS Display User Guide

Revision 0.1 Preliminary

AMLOGIC, Inc.

3930 Freedom Circle Santa Clara, CA 95054

U.S.A. https://www.sodocs.net/doc/fa14561333.html,

AMLOGIC reserves the right to change any information described herein at any time without notice.

AMLOGIC assumes no responsibility or liability from use of such information.

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Table of Content

1 GENERAL DESCRIPTION ...................................................................................................................................... 4 2

LVDS DATA OUTPUT .............................................................................................................................................. 5 2.1 LVDS D ATA P ORTS ............................................................................................................................................... 5 2.2 LVDS L OGIC S ETTING .......................................................................................................................................... 5 2.2.1 LVDS Data Mapping ..................................................................................................................................... 5 2.2.2 LVDS PN Swapping ...................................................................................................................................... 6 3

LCD BASIC ................................................................................................................................................................. 6 3.1 D ISPLAY A REA D EFINITION ................................................................................................................................... 6 3.2 P ANEL A SPECT R ATIO ........................................................................................................................................... 7 3.3 P ANEL I NTERFACE ................................................................................................................................................. 7 4 LCD TIMING . (7)

4.1 P IXEL C LOCK C ALCULATE ..................................................................................................................................... 7 4.2 P IXEL C LOCK S PREAD S PECTRUM ......................................................................................................................... 8 4.3 S YNCHRONIZATION S IGNAL D EFINITION ............................................................................................................... 8 5 LCD EFFECT . (9)

5.1 B ASE S HIFTING ...................................................................................................................................................... 9 5.2 C O -EFFECTIVE FACTOR CORRECTION ................................................................................................................... 10 5.3 G AMMA LOOKUP TABLE CORRECTION ................................................................................................................. 10 6 ANDROID DRIVER. (11)

6.1 U BOOT D RIVER .................................................................................................................................................... 11 6.2 K ERNEL D RIVER .................................................................................................................................................. 11 7 REGISTER ADDRESS MAPPING (11)

7.1 R EGISTER ADDRESS MAPPING .............................................................................................................................. 11 7.2 R EGISTER OPERATION FOR SERIAL DEBUGGING ................................................................................................... 11 8 REGISTER DESCRIPTIONS (12)

8.1 LVDS D ATA O UTPUT .......................................................................................................................................... 12 8.2 V IDEO C LOCK ...................................................................................................................................................... 13 8.3 S YNCHORIZATION S IGNAL ................................................................................................................................... 13 8.4 RGB D ATA E FFECT (14)

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Revision History

Revision Number Revised Date By

Changes 0.1 April.11, 2012 Evoke Zhang 1st

Draft Version

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1 General Description

Amlogic AML8726-MX is a highly integrated multimedia application processor SoC for Multimedia Internet Device (MID), tablet and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics subsystem and a state-of-the-art video decoding engine together with all major peripherals.

AML8726-MX integrates three LCD panel timing controllers: TTL, LVDS, and mLVDS. TTL should be used with TTL type LCD panel, LVDS is for LVDS type LCD panel, and mLVDS is for mini-LVDS type LCD panel.

This document is a user guide of AML8726-MX LVDS interface for LVDS LCD panel timing control only. This document describes:

● LVDS data output ● LCD Basic ● LCD Timing ● LCD Effect ● Android Driver

● Register address mapping ● Register description

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2 LVDS Data output

2.1 L VDS Data Ports

AML8726-MX has 10bits LVDS data output. All LVDS data signals are connected to a series of LVDS physical ports. The physical ports are controlled by register LVDS_PHY_CNTL4, which listed in Table 1.

Table 1. LVDS physical ports control

Signal Name Physical ports control bit Description

LVDS 0+/- LVDS_PHY_CNTL4 bit[0] set 1 to enable port set 0 to disable port LVDS 1+/- LVDS_PHY_CNTL4 bit[1] LVDS 2+/- LVDS_PHY_CNTL4 bit[2] LVDS 3+/- LVDS_PHY_CNTL4 bit[3] LVDS 4+/- LVDS_PHY_CNTL4 bit[4] LVDS clk+/-

LVDS_PHY_CNTL4 bit[5]

When required RGB888 data for a 8bits LVDS panel, the register LVDS_PHY_CNTL4 need setting to 0x2f, and set the register to 0x27 will output RGB666 data for 6bits LVDS signals.

2.2 L VDS Logic Setting

2.2.1 LVDS Data Mapping

AML8726-MX support both JEDIA and VESA mode LVDS Data Mapping. They are illustrated in

VIDEO_ON_PIXEL define internal image data horizontal starting position, VIDEO_ON_LINE define internal image data vertical starting position, they are both decided to AML8726-MX internal hardware, and can not be modified.

2.3 P anel Aspect Ratio

Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.

This value is controlled by the members of lcd_basic struct named screen_ratio_width and screen_ratio_height, the quotient of screen_ratio_width dividing screen_ratio_height must match panel active area ’s width-height ratio.

For example:

● panel active area is 154.08(W)*85.92(H)(unit: mm)

● panel active area ’s width-height ratio is 1.79, approach to 16:9, so we can set as below:

. screen_ratio_width = 16, . screen_ratio_height = 9,

2.4 P anel Interface

The Panel Interface information also must be set in lcd_basic struct, the example is as below:

.lcd_type = LCD_DIGITAL_LVDS, .lcd_bits = 8, //8 or 6

3 LCD Timing

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3.1 P ixel Clock Calculate

AML8726-MX uses four parameters to set LVDS panel pixel clock, such as M, N, OD and div. They are contained in the members named pll_ctrl and div_ctrl of lcd_timing struct. The parameters are illustrated in Table 5.

Table 5. pixel clock parameter

Item Symbol Range

pll_ctrl[8:0] M 750M<(M*24/N)<1500M pll_ctrl[13:9] N 1~4

pll_ctrl[17:16] OD 0~2

div_ctrl[7:4]

div

0~5

The pixel clock(clk) calculates with below formula:

clk = M*XTAL/(N*2OD

*(div+1)*7) //generally speaking, XTAL=24M

For example:

● .pll_ctrl=0x10221,

.div_ctrl=0x18813, .clk_ctrl=0x1111,

● Then M=33, N=1, OD=1, div=1. ● clk=33*24/(1*2*2*7)=28.3MHz.

Pixel clock can be real-time changed by editing the registers HHI_VIID_PLL_CNTL, HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.

3.2 P ixel Clock Spread Spectrum

The clock spread spectrum function is controlled by parameter ss_level, which is assigned to clk_ctrl[19:16] of lcd_timing struct. The range of ss_level is 0~5, means clock spread spectrum width. The example is as below:

.clk_ctrl=0x31111, //ss_level=3, the clock spread spetrum width is 3%. .

Figure 1. LVDS Data Mapping

Mapping 0 (JEDIA Mode):

Mapping 1 (VESA Mode):

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The member of lcd_lvds_phy_control struct named lvds_repack controls the LVDS Data Mapping as Table 2.

Table 2. LVDS Data Mapping Control

Item Value LVDS Data Mapping

lvds_repack

0 JEDIA 1

VESA

LVDS data mapping can be changed by editing the register LVDS_PACK_CNTL_ADDR real-time. For details please see the registers description in Chapter 8.

3.2.1 LVDS PN Swapping

The member of lcd_lvds_phy_control struct named pn_swap controls the LVDS PN Swapping as Table 3.

Table 3. LVDS PN Swapping Control

Item

Value LVDS PN Swapping pn_swap

0 normal 1

p/n swap

LVDS p/n swapping can be changed by editing the register LVDS_PACK_CNTL_ADDR real-time. For details please see the registers description in Chapter 8.

4 LCD Basic

4.1 D isplay Area Definition

The display area are grids of pixels that can be divided into horizontal and vertical. They are illustrated in VIDEO_ON_PIXEL define internal image data horizontal starting position, VIDEO_ON_LINE define internal image data vertical starting position, they are both decided to AML8726-MX internal hardware, and can not be modified.

4.2 P anel Aspect Ratio

Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.

This value is controlled by the members of lcd_basic struct named screen_ratio_width and screen_ratio_height, the quotient of screen_ratio_width dividing screen_ratio_height must match panel active area ’s width-height ratio.

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For example:

● panel active area is 154.08(W)*85.92(H)(unit: mm)

● panel active area ’s width-height ratio is 1.79, approach to 16:9, so we can set as below:

. screen_ratio_width = 16, . screen_ratio_height = 9,

4.3 P anel Interface

The Panel Interface information also must be set in lcd_basic struct, the example is as below:

.lcd_type = LCD_DIGITAL_LVDS, .lcd_bits = 8, //8 or 6

5 LCD Timing

5.1 P ixel Clock Calculate

AML8726-MX uses four parameters to set LVDS panel pixel clock, such as M, N, OD and div. They are contained in the members named pll_ctrl and div_ctrl of lcd_timing struct. The parameters are illustrated in Table 5.

Table 5. pixel clock parameter

Item Symbol Range

pll_ctrl[8:0] M 750M<(M*24/N)<1500M

pll_ctrl[13:9] N 1~4 pll_ctrl[17:16] OD 0~2

div_ctrl[7:4]

div

0~5

The pixel clock(clk) calculates with below formula:

clk = M*XTAL/(N*2OD

*(div+1)*7) //generally speaking, XTAL=24M

For example:

● .pll_ctrl=0x10221,

.div_ctrl=0x18813, .clk_ctrl=0x1111,

● Then M=33, N=1, OD=1, div=1. ● clk=33*24/(1*2*2*7)=28.3MHz.

Pixel clock can be real-time changed by editing the registers HHI_VIID_PLL_CNTL, HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.

5.2 P ixel Clock Spread Spectrum

The clock spread spectrum function is controlled by parameter ss_level, which is assigned to clk_ctrl[19:16] of lcd_timing struct. The range of ss_level is 0~5, means clock spread spectrum width. The example is as below:

.clk_ctrl=0x31111, //ss_level=3, the clock spread spetrum width is 3%. .

Figure 2. Display Area

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For example:

● A TTL panel ’s timing are defined as below in Table 4: (These timing are available in panel specification.)

Table 4. Timing

Item

Value Unit Related Parameter of AML8726-MX TCON Signal

Horizontal Display Area 800 pixel h_active

Hsync

(low active) HS period time 1056 pixel h_period HS pulse width 10 pixel HS back porch 60

pixel Horizontal back porch

Vertical display area 480 line v_active Vsync

(low active)

VS period time 535 line v_period VS pulse width 4

line

VS back porch

20 line

Vertical back porch

The display parameter need to set as below: #define H_ACTIVE 800 #define V_ACTIVE 480 #define H_PERIOD 1056 #define V_PERIOD 525 #define VIDEO_ON_PIXEL 80 #define VIDEO_ON_LINE 32

H_ACTIVE and V_ACTIVE define the area that real image displays, H_PERIOD and V_PERIOD define horizontal and vertical total timing, they are applied to calculate line frequence and frame rate.

VIDEO_ON_PIXEL define internal image data horizontal starting position, VIDEO_ON_LINE define internal image data vertical starting position, they are both decided to AML8726-MX internal hardware, and can not be modified.

5.3 P anel Aspect Ratio

Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.

This value is controlled by the members of lcd_basic struct named screen_ratio_width and screen_ratio_height, the quotient of screen_ratio_width dividing screen_ratio_height must match panel active area ’s width-height ratio.

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For example:

● panel active area is 154.08(W)*85.92(H)(unit: mm)

● panel active area ’s width-height ratio is 1.79, approach to 16:9, so we can set as below:

. screen_ratio_width = 16, . screen_ratio_height = 9,

5.4 P anel Interface

The Panel Interface information also must be set in lcd_basic struct, the example is as below:

.lcd_type = LCD_DIGITAL_LVDS, .lcd_bits = 8, //8 or 6

6 LCD Timing

6.1 P ixel Clock Calculate

AML8726-MX uses four parameters to set LVDS panel pixel clock, such as M, N, OD and div. They are contained in the members named pll_ctrl and div_ctrl of lcd_timing struct. The parameters are illustrated in Table 5.

Table 5. pixel clock parameter

Item Symbol Range

pll_ctrl[8:0] M 750M<(M*24/N)<1500M

pll_ctrl[13:9] N 1~4 pll_ctrl[17:16] OD 0~2

div_ctrl[7:4]

div

0~5

The pixel clock(clk) calculates with below formula:

clk = M*XTAL/(N*2OD

*(div+1)*7) //generally speaking, XTAL=24M

For example:

● .pll_ctrl=0x10221,

.div_ctrl=0x18813, .clk_ctrl=0x1111,

● Then M=33, N=1, OD=1, div=1. ● clk=33*24/(1*2*2*7)=28.3MHz.

Pixel clock can be real-time changed by editing the registers HHI_VIID_PLL_CNTL, HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.

6.2 P ixel Clock Spread Spectrum

The clock spread spectrum function is controlled by parameter ss_level, which is assigned to clk_ctrl[19:16] of lcd_timing struct. The range of ss_level is 0~5, means clock spread spectrum width. The example is as below:

.clk_ctrl=0x31111, //ss_level=3, the clock spread spetrum width is 3%.

6.3 S ynchronization Signal Definition

AML8726-MX displays the image with horizontal starting at 80 pixels, vertical starting at 32 lines. they are according to display parameter VDIEO_ON_PIXEL and VIDEO_ON_LINE setting, and can not be modified.

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LVDS panel generally has three synchronization signals to control display, such as Hsync, Vsync and DE. The signals are illustrated in

VIDEO_ON_PIXEL define internal image data horizontal starting position, VIDEO_ON_LINE define internal image data vertical starting position, they are both decided to AML8726-MX internal hardware, and can not be modified.

6.4 P anel Aspect Ratio

Set the right value of Panel Aspect Ratio to ensure the length-to-width ratio of OSD display.

This value is controlled by the members of lcd_basic struct named screen_ratio_width and screen_ratio_height, the quotient of screen_ratio_width dividing screen_ratio_height must match panel active area ’s width-height ratio.

For example:

● panel active area is 154.08(W)*85.92(H)(unit: mm)

● panel active area ’s width-height ratio is 1.79, approach to 16:9, so we can set as below:

. screen_ratio_width = 16, . screen_ratio_height = 9,

6.5 P anel Interface

The Panel Interface information also must be set in lcd_basic struct, the example is as below:

.lcd_type = LCD_DIGITAL_LVDS, .lcd_bits = 8, //8 or 6

7 LCD Timing

7.1 P ixel Clock Calculate

AML8726-MX uses four parameters to set LVDS panel pixel clock, such as M, N, OD and div. They are contained in the members named pll_ctrl and div_ctrl of lcd_timing struct. The parameters are illustrated in Table 5.

Table 5. pixel clock parameter

Item

Symbol Range

pll_ctrl[8:0] M 750M<(M*24/N)<1500M pll_ctrl[13:9] N 1~4 pll_ctrl[17:16] OD 0~2 div_ctrl[7:4]

div

0~5

The pixel clock(clk) calculates with below formula:

clk = M*XTAL/(N*2OD

*(div+1)*7) //generally speaking, XTAL=24M

For example:

● .pll_ctrl=0x10221,

.div_ctrl=0x18813, .clk_ctrl=0x1111,

● Then M=33, N=1, OD=1, div=1. ● clk=33*24/(1*2*2*7)=28.3MHz.

Pixel clock can be real-time changed by editing the registers HHI_VIID_PLL_CNTL, HHI_VIID_DIVIDER_CNTL. For details please see the registers description in Chapter 9.

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7.2 P ixel Clock Spread Spectrum

The clock spread spectrum function is controlled by parameter ss_level, which is assigned to clk_ctrl[19:16] of lcd_timing struct. The range of ss_level is 0~5, means clock spread spectrum width. The example is as below:

.clk_ctrl=0x31111, //ss_level=3, the clock spread spetrum width is 3%.

3. In AML8726-MX, the DE signal is generated by Encoder internally.

Figure 3. Synchronization Signals

For example:

● We still use the timing defined in Table 4.

● The synchronization signals are assigned to lcd_timing struct members in display driver as follow:

Hsync – sth1, Vsync – stv1.

● The display parameters need to set as below:

.sth1_hs_addr = 20, //80-60 //horizontal start- horizontal_back_porch .sth1_he_addr = 30, //80-60+10 //horizontal start- horizontal_back_porch+hs_pulse_width

.stv1_vs_addr = 12, //32-20 //vertical start-vertical_back_porch .stv1_ve_addr = 15, //32-20+4-1 //vertical start-vertical_back_porch+vs_pulse_width-1

The Hsync and Vsync signals can be changed by editing the Encoder registers real-time. For details please see the registers description in Chapter 8.

8 LCD Effect

AML8726-MX integrates a build-in data correction engine to compensate nonlinear LCD panel display characteristics and improve the display quality.

All data correction is processed in RGB color gamut only. Each pixel RGB data in processing is 10 bit for each color channel comparing to the 8-bit output to panel.

The data correction process includes three steps: 1. Base shifting

2. Co-effective factor correction

3. Gamma lookup table correction

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The data correction data processing is illustrated in Figure .

Figure 5. RGB Data Correction Process

Corrected Red Data

Green

Blue

RGB_BASE_ADDR[9:0]

RGB_COEFF_ADDR[10:0]

Corrected Green Data

Corrected Blue Data

Red

Blue Gamma Lookup Table

Green Gamma Lookup Table

Red Gamma Lookup Table

8.1 B ase Shifting

Base shifting is the first step of gamma correction to correct the luminance of the image. Each pixel RGB data will add the value of the base shifting value in RGB_BASE_ADDR[9:0].

Please notice:

1. The effective values of RGB_BASE_ADDR[9:0] are from -512 to +511.

2. The values of RGB_BASE_ADDR[9:0] will be used for all RGB channels at the same time.

8.2 C o-effective factor correction

Co-effective factor correction is the second step to do linear gamma correction of the image. Each pixel RGB data will multiply the value of co-effective factor in RGB_COEFF_ADDR[10:0].

Please notice:

1. The effective value of RGB_COEFF_ADDR[10:0] is from 0 to 1.999023.

The value of RGB_COEFF_ADDR[10:0] will be used for all RGB channels at the same time.

8.3 G amma lookup table correction

Gamma lookup table correction is the last step to do non-linear gamma correction based on color mapping using lookup table.

AML8726-MX integrates 768 10-bit registers to store gamma lookup table used by step 3 of gamma correction. The registers are divided into 3 blocks. Each block has 256 10-bit registers to store one color channel gamma lookup table values:

● Red lookup table registers (R_LUT) ● Green lookup table registers (G_LUT) ● Blue lookup table registers (B_LUT)

The gamma table is set as below.

static void t13_setup_gama_table(tcon_conf_t *pConf) {

int i;

const unsigned short gamma_adjust[256] = {

0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,

32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63, …… 248,249,250,251,252,253,254,255 };

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for (i=0; i<256; i++) {

pConf->GammaTableR[i] = gamma_adjust[i] << 2; pConf->GammaTableG[i] = gamma_adjust[i] << 2; pConf->GammaTableB[i] = gamma_adjust[i] << 2; } }

Gamma correction is controlled by the member of panel parameter named gamma_cntl_port.(set 1 to enable gamma correction)

.gamma_cntl_port = (1 << LCD_GAMMA_EN),

gamma correction can be enabled/disabled by editing the register GAMMA_CNTL_PORT real-time. For details please see the registers description in Chapter 9.

9 Android Driver

9.1 U boot Driver

Amlogic provides Panel Parameter files for uboot. In Amlogic reference code, the directory is

[uboot root]/board/amlogic/[board directory]/

It recommends that software creates a single C type source code file for each panel.

9.2 K ernel Driver

Amlogic provides Panel Parameter files for Kernel. In Amlogic reference code, the directory is

[kernel root]/customer/boards/

It recommends that software creates a single C type source code file for each panel.

10 Register Address Mapping

10.1 Register address mapping

The register addresses in this document are provided as address offset. Address mapping is needed to convert register address offset to the physical register address.

The basic formula of address mapping is:

REG_ADDR = BASE_ADDR + (REG_OFFSET << 2)

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where:

REG_ADDR: physical register address that software can access the register BASE_ADDR: the base address of the address bus REG_OFFSET: the register address offset

The value of base address (BASE_ADDR) may be different in different software implementation. In Amlogic ported Linux kernel and the boot loader uBoot, the base addresses are:

Linux Kernel: 0xF1100000 uboot: 0xC1100000

Software needs to choose BASE_ADDR according implementation environment.

10.2 Register operation for serial debugging

The register can be read or write for serial debugging.

uboot: read: md REG_ADDR write: mw REG_ADDR REG_VAL Linux Kernel: read: echo “REG_OFFSET ” > /sys/class/i2c/cbus_reg write: echo “w REG_OFFSET REG_VAL ” > /sys/class/i2c/cbus_reg

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11 Register Descriptions

11.1 LVDS Data Output

Table 6. LVDS_PHY_CNTL4 Register Definition

Name LVDS_PHY_CNTL4 Offset 0x14e0

Width 32-bit

Bit Name R/W Default Description 31:6 -

- - Reserved

5 LVDS_MDR_PU[5] R/W 0 set 1 to enable LVDS clk channel output 4 LVDS_MDR_PU[4] R/W 0 set 1 to enable LVDS data channel 4 output 3 LVDS_MDR_PU[3] R/W 0 set 1 to enable LVDS data channel 3 output 2 LVDS_MDR_PU[2] R/W 0 set 1 to enable LVDS data channel 2 output 1 LVDS_MDR_PU[1] R/W 0 set 1 to enable LVDS data channel 1 output 0

LVDS_MDR_PU[0]

R/W

set 1 to enable LVDS data channel 0 output

Table 7. LVDS_PACK_CNTL_ADDR Register Definition

Name LVDS_PACK_CNTL_ADDR Offset 0x14d0 Width

32-bit

Bit Name R/W Default Description 31:6 - - - Reserved

5 PN_SWP R/W 0 LVDS PN Swapping control 0: normal 1: swap 4:2 -

- - Reserved

1:0

LVDS_REPACK

R/W

LVDS Data Mapping Control 0: JEIDA mode 1: VESA mode

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11.2 Video Clock

Table 8. HHI_VIID_CLK_DIV Register Definition

Name HHI_VIID_PLL_CNTL Offset

0x1047 Width 32-bit

Bit Name R/W Default Description 31:18 - - - Reserved

17:16 OD R/W 0 Video clock parameter OD, see Chapter 4.1 for detail. 15:14 - - - Reserved

13:9 N R/W 0 Video clock parameter N, see Chapter 4.1 for detail. 8:0

M R/W

Video clock parameter M, see Chapter 4.1 for detail.

Table 9. HHI_VID_DIVIDER_CNTL Register Definition

Name HHI_VIID_PLL_CNTL Offset

0x1066 Width 32-bit

Bit Name R/W Default Description 31:7 - - - Reserved

6:4 PRE_SEL R/W 0 Video clock parameter div, see Chapter 4.1 for detail. 3:0

- -

-

Reserved

11.3 Synchorization Signal

Table 10. ENCL_VIDEO_HSO_BEGIN Register Definition

Name ENCL_VIDEO_HSO_BEGIN Offset 0x1cb5 Width 32-bit

Bit Name

R/W Default Description 31:0

ENCL_VIDEO_HSO_BEGIN

R/W

0 Hsync signal horizontal start pixel position.

Table 11. ENCL_VIDEO_HSO_END Register Definition

Name

ENCL_VIDEO_HSO_END Offset 0x1cb6 Width 32-bit

Bit Name

R/W Default Description 31:0

ENCL_VIDEO_HSO_END

R/W

0 Hsync signal horizontal end pixel position.

Table 12. ENCL_VIDEO_VSO_BLINE Register Definition

Name

ENCL_VIDEO_VSO_BLINE Offset 0x1cb9 Width 32-bit

Bit Name

R/W Default Description 31:0

ENCL_VIDEO_VSO_BLINE

R/W

0 Vsync signal vertical start line position

Table 13. ENCL_VIDEO_VSO_ELINE Register Definition

Name

ENCL_VIDEO_VSO_ELINE Offset 0x1cba Width 32-bit

Bit Name

R/W Default Description 31:0

ENCL_VIDEO_VSO_ELINE

R/W

0 Vsync signal vertical end line position.

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11.4 RGB Data Effect

Table 14. L_GAMMA_CNTL_PORT Register Definition

Name L_GAMMA_CNTL_PORT Offset 0x1400

Width 32-bit

Bit Name R/W Default Description 31:1 -

- - Reserved 0

GAMMA_EN

R/W

0 Gamma correction enable

0: disable gamma correction 1: enable gamma correction

Table 15. L_RGB_BASE_ADDR Register Definition

Name L_RGB_BASE_ADDR Offset 0x1405 Width 32-bit

Bit Name R/W Default Description 31:10 -

- - Reserved 9:0

RGB_BASE_ADDR

R/W

0 Gamma correction base shifting value

Table 16. L_RGB_COEFF_ADDR Register Definition

Name

L_RGB_COEFF_ADDR Offset 0x1406 Width 32-bit

Bit Name R/W Default Description 31:11 -

- - Reserved 10:0

RGB_COEFF_ADDR

R/W

0 Gamma correction coefficient value

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补上6个橙色菜谱属性

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