General Description
The MAX5821 is a dual, 10-bit voltage-output, digital-to-analog converter (DAC) with an I 2C*-compatible,2-wire interface that operates at clock rates up to 400kHz.The device operates from a single 2.7V to 5.5V supply 115μA at V DD = 3.6V. A power-down mode decreases current consumption to less than 1μA. The MAX5821 fea-tures three software-selectable power-down output impedances: 100k ?, 1k ?, and high impedance. Other features include internal precision rail-to-rail output buffers and a power-on reset (POR) circuit that powers up the DAC in the 100k ?power-down mode.
The MAX5821 features a double-buffered I 2C-compatible serial interface that allows multiple devices to share a sin-gle bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5821 minimizes digital noise feedthrough by discon-necting the clock (SCL) signal from the rest of the device when an address mismatch is detected.
The MAX5821 is specified over the extended temperature range of -40°C to +85°C and is available in a miniature 8-pin μMAX ?package. Refer to the MAX5822 data sheet for the 12-bit version and the MAX5820 data sheet for the 8-bit version.
Applications
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources Programmable Attenuation VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Operated Instrumentation
Features
?Ultra-Low Supply Current
115μA at V DD = 3.6V 135μA at V DD = 5.5V
?300nA Low-Power Power-Down Mode ?Single 2.7V to 5.5V Supply Voltage ?Fast 400kHz I 2C-Compatible 2-Wire Serial Interface
?Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers ?Rail-to-Rail Output Buffer Amplifiers
?Three Software-Selectable Power-Down Output Impedances
100k ?, 1k ?, and High Impedance ?Read-Back Mode for Bus and Data Checking ?Power-On Reset to Zero ?8-Pin μMAX Package
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
________________________________________________________________Maxim Integrated Products 1
Pin Configuration
Ordering Information
Typical Operating Circuit
19-2316; Rev 1; 2/05
For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at https://www.sodocs.net/doc/0015829201.html,.
μMax is a registered trademark of Maxim Integrated Products, Inc.*Purchase of I 2C components from Maxim Integrated Products,Inc., or one of its sublicensed Associate Companies, conveys a license under the Philips I 2C Patent Rights to use these compo-nents in an I 2C system, provided that the system conforms to the I 2C Standard Specification.
M A X 5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V DD = +2.7V to +5.5V, GND = 0, V REF = V DD , R L = 5k ?, C L = 200pF, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V DD = +5V, T A = +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
V DD , SCL, SDA to GND............................................-0.3V to +6V OUT_, REF, ADD to GND..............................-0.3V to V DD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (T A = +70°C)
8-Pin μMAX (derate 4.5mW above +70°C)...................362mW
Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Maximum Junction Temperature.....................................+150°C Lead Temperature (soldering, 10s).................................+300°C
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________3
ELECTRICAL CHARACTERISTICS (continued)
M A X 5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 4_______________________________________________________________________________________
INTEGRAL NONLINEARITY
vs. INPUT CODE
M A X 5821 t o c 01
INPUT CODE
I N L (L S B )
768
512256
-0.75-0.50-0.2500.250.500.751.00-1.00
1024
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
M A X 5821 t o c 02
SUPPLY VOLTAGE (V)
I N L (L S B )
4.8
4.1
3.4
0.250.500.751.001.2502.7
5.5
INTEGRAL NONLINEARITY vs. TEMPERATURE
M A X 5821 t o c 03
TEMPERATURE (°C)
I N L (L S B )
60
35
10
-15
0.25
0.50
0.75
1.00
1.25
0-40
85
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
M A X 5821 t o c 04
INPUT CODE
D N L (L S B )
768
512256
-0.75-0.50-0.2500.25
0.50
0.751.00
-1.00
1024
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
M A X 5821 t o c 05
SUPPLY VOLTAGE (V)
D N L (L S B )
4.8
4.1
3.4
-0.4-0.3
-0.2-0.10-0.5
2.7
5.5
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
M A X 58
21 t o c 06
TEMPERATURE (°C)
D N L (L S B )
60
35
10
-15
-0.4
-0.3
-0.2
-0.1
-0.5
-40
85
Typical Operating Characteristics
(V DD = +5V, R L = 5k ?, T A = +25°C.)
ELECTRICAL CHARACTERISTICS (continued)
(V DD = +2.7V to +5.5V, GND = 0, V REF = V DD , R L = 5k ?, C L = 200pF, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V = +5V, T = +25°C.) (Note 1)
Note 2:Static specifications are tested with the output unloaded.Note 3:Linearity is guaranteed from codes 28 to 995.Note 4:Offset and gain error limit the FSR.
Note 5:Guaranteed by design. Not production tested.
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________5
ZERO-CODE ERROR vs. SUPPLY VOLTAGE
M A X 5821 t o c 07
SUPPLY VOLTAGE (V)
Z E R O -C O D E E R R O R (m V )
4.8
4.1
3.4
2
468100
2.7
5.5
NO LOAD
ZERO-CODE ERROR vs. TEMPERATURE
M A X 5821 t o c 08
TEMPERATURE (°C)
Z E R O -C O D E E R R O R (m V )
60
35
10
-15
2
468100-40
85
NO LOAD
GAIN ERROR vs. SUPPLY VOLTAGE
M A X 5821 t o c 09
SUPPLY VOLTAGE (V)
G A I N E R R O R (%F S R )
4.8
4.1
3.4
-0.4
-0.8
-1.2
-1.6-2.0
2.7
5.5
NO LOAD
GAIN ERROR vs. TEMPERATURE
M A X 5821 t o c 10
TEMPERATURE (°C)
G A I N E R R O R (%F S R )
60
35
10
-15
-0.4
-0.8-1.2-1.6-2.00
-40
85
NO LOAD
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
OUTPUT SOURCE CURRENT (mA)
D A C O U T P U T V O L T A G
E (V )
8
6
4
2
1
2345600
10
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
OUTPUT SINK CURRENT (mA)
D A C O U T P U T V O L T A G
E (V )
8
6
4
2
0.5
1.0
1.5
2.0
2.5
00
10
SUPPLY CURRENT vs. INPUT CODE
M A X 5821 t o c 13
INPUT CODE
S U P P L Y C U R R E N T (μA )
820
615
410
205
120140160180100
1024
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
S U P P L Y C U R R E N T (μA )
60
35
10
-15
120
140
160180100
-40
85
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
S U P P L Y C U R R E N T (μA )
4.8
4.1
3.4
120
140
160
180
100
2.7
5.5
Typical Operating Characteristics (continued)
(V DD = +5V, R L = 5k ?, T A = +25°C.)
M A X 5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 6
_______________________________________________________________________________________
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
M A X 5821 t o c 16
SUPPLY VOLTAGE (V)
P O W E R -D O W N S U P P L Y C U R R E N T (n A )
4.8
4.1
3.4
100
200
300
400
500
02.7
5.5
POWER-UP GLITCH
MAX5821 toc17
100μs/div
V DD
OUT_
5V
10mV/div
EXITING SHUTDOWN
2μs/div
OUT_
500mV/div
C LOA
D = 200pF COD
E = 200 hex
MAJOR CARRY TRANSITION
(POSITIVE)
2μs/div
OUT_
5mV/div C LOAD = 200pF
R L = 5k ?
CODE = 1FF hex TO 200 hex MAJOR CARRY TRANSITION
(NEGATIVE)
2μs/div
OUT_5mV/div C LOAD = 200pF
R L = 5k ?
CODE = 200 hex TO 1FF hex SETTLING TIME (POSITIVE)
2μs/div
OUT_
500mV/div
C LOA
D = 200pF
CODE = 100 hex TO 300 hex SETTLING TIME (NEGATIVE)
2μs/div
OUT_
500mV/div
C LOA
D = 200pF
CODE = 300 hex TO 100 hex DIGITAL FEEDTHROUGH
40μs/div
OUT_
2mV/div C LOAD = 200pF f SCL = 12kHz CODE = 000 hex
SCL 2V/div CROSSTALK
MAX5821 toc24
4μs/div
V
OUTB
1mV/div
V OUTA 2V/div
Typical Operating Characteristics (continued)
(V DD = +5V, R L = 5k ?, T A = +25°C.)
Note 6:The ability to drive loads greater than 5k ?is not implied.
Detailed Description
The MAX5821 is a dual, 10-bit, voltage-output DAC with an I 2C/SMBus?-compatible 2-wire interface. The device consists of a serial interface, power-down cir-cuitry, dual input and DAC registers, two 10-bit resistor string DACs, two unity-gain output buffers, and output resistor networks. The serial interface decodes the address and control bits, routing the data to the proper input or DAC register. Data can be directly written to the DAC register, immediately updating the device out-put, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered.
DAC Operation
The MAX5821 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5821’s input coding is straight binary, with the output voltage given by the following equation:
where N = 10 (bits), and D = the decimal value of the input code (0 to 1023).
Output Buffer
The MAX5821 analog outputs are buffered by preci-sion, unity-gain followers that slew 0.5V/μs. Each buffer output swings rail-to-rail, and is capable of driving 5k ?in parallel with 200pF. The output settles to ±0.5LSB within 4μs.
Power-On Reset
The MAX5821 features an internal POR circuit that ini-tializes the device upon power-up. The DAC registers are set to zero scale and the device is powered down,
to GND through the 100k ?termination resistor.Following power-up, a wake-up command must be initi-ated before any conversions are performed.
Power-Down Modes
The MAX5821 has three software-controlled low-power power-down modes. All three modes disable the output buffers and disconnect the DAC resistor strings from REF, reducing supply current draw to 1μA and the ref-erence current draw to less than 1μA. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1k ?termination resistor. In power-down mode 2, the device output is internally pulled to GND by a 100k ?termination resistor. Table 1 shows the power-down mode command words.
Upon wake-up, the DAC output is restored to its previ-ous value. Data is retained in the input and DAC regis-ters during power-down mode.
Digital Interface
The MAX5821 features an I 2C/SMBus-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). The MAX5821 is SMBus com-patible within the range of V DD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5821 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5821 is a transmit/receive slave-only device, rely-ing upon a master to generate a clock signal. The mas-ter (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5821 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (S r ) condition and a STOP (P) condition. Each word transmitted over the
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________7
SMBus is a trademark of Intel Corporation.
M A X 5821
bus is 8 bits long and is always followed by an acknowledge clock pulse.
The MAX5821 SDA and SCL drivers are open-drain out-puts, requiring a pullup resistor to generate a logic high voltage (see the Typical Operating Circuit). Series resistors R S are optional. These series resistors protect the input stages of the MAX5821 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). Both SDA and SCL idle high when the I 2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issu-ing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5821. The master terminates transmission by issuing a not acknowledge followed by a STOP condition (see Acknowledge Bit (ACK)). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active.When a STOP condition or incorrect address is detect-ed, the MAX5821 internally disconnects SCL from the serial interface until the next START condition, minimiz-ing digital noise and feedthrough.
Early STOP Conditions
The MAX5821 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I 2C format; at least one clock pulse must separate any START and STOP conditions.
Repeated START Conditions
A repeated START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I 2C devices and does not want to relinquish control of the bus. The MAX5821 seri-al interface supports continuous write operations with or without an S r condition separating them. Continuous read operations require S r conditions because of the change in direction of data flow.
Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 8
_______________________________________________________________________________________
Figure 1. 2-Wire Serial Interface Timing Diagram
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5821 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data,the MAX5821 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuc-cessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communica-tion at a later time.
Slave Address
A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address (Figure 4). When idle, the MAX5821
waits for a START condition followed by its slave address. The serial interface compares each address value bit-by-bit, allowing the interface to power down immediately if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W ) bit.R/W indicates whether the master is writing to or read-ing from the MAX5821 (R/W = 0 selects the write condi-tion, R/W = 1 selects the read condition). After receiving the proper address, the MAX5821 issues an
ACK by pulling SDA low for one clock cycle.
The MAX5821 has four different factory/user-pro-grammed addresses (Table 2). Address bits A6through A1 are preset, while A0 is controlled by ADD.Connecting ADD to GND sets A0 = 0. Connecting ADD to V DD sets A0 = 1. This feature allows up to four
In write mode (R/W = 0), data that follows the address byte controls the MAX5821 (Figure 5). Bits C3–C0 con-figure the MAX5821 (Table 3). Bits D9–D0 are DAC data. Bits S0 and S1 are sub-bits and are always 0.Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the write cycle must be repeated. Figure 6 shows two example-write data sequences.
Extended Command Mode
The MAX5821 features an extended command mode that is accessed by setting C3–C0 = 1 and D9–D6 = 0.
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
_______________________________________________________________________________________
9
Figure 2. START and STOP Conditions
Figure 3. Early STOP conditions
M A X 5821
The next command word writes to the power-down reg-isters (Figure 7). Setting bits A or B to 1 sets that DAC to the selected power-down mode based on the states of PD0 and PD1 (Table 1). Any combination of the DACs can be controlled with a single write sequence.Read Data Format
In read mode (R/W = 1), the MAX5821 writes the con-tents of the DAC register to the bus. The direction of data flow reverses following the address acknowledge by the MAX5821. The device transmits the first byte of data, waits for the master to acknowledge, then trans-mits the second byte. Figure 8 shows an example-read data sequence.
I 2C Compatibility
The MAX5821 is compatible with existing I 2C systems.SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typi-cal I 2C application. The communication protocol sup-ports the standard I 2C 8-bit communications. The general call address is ignored. The MAX5821 address is compatible with the 7-bit I 2C addressing protocol only. No 10-bit address formats are supported.
Digital Feedthrough Suppression
When the MAX5821 detects an address mismatch, the serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected.
Applications Information
Digital Inputs and Interface Logic
The MAX5821 2-wire digital interface is I 2C/SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces, such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels.
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low impedance. Bypass V DD with a 0.1μF capacitor to ground as close to the device as possible.
Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 10
______________________________________________________________________________________
Figure 6. Example-Write Command Sequences
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
______________________________________________________________________________________11
M A X 5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC 12
______________________________________________________________________________________
Figure 8. Example-Read Word Data Sequence
Functional Diagram
Chip Information
TRANSISTOR COUNT: 11,186PROCESS: BiCMOS
MAX5821
Dual, 10-Bit, Low-Power, 2-Wire, Serial
Voltage-Output DAC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________13?2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to https://www.sodocs.net/doc/0015829201.html,/packages .)