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A neural network accelerator for mobile applicati

A neural network accelerator for mobile applicati
A neural network accelerator for mobile applicati

D. Y. Kim et al.: A Neural Network Accelerator for Mobile Application Processors
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A Neural Network Accelerator for Mobile Application Processors
Doo Young Kim, Jin Min Kim, Hakbeom Jang, Jinkyu Jeong, and Jae W. Lee, Member, IEEE
Abstract — Today’s mobile consumer electronics devices, such as smartphones and tablets, are required to execute a wide variety of applications efficiently. To this end modern application processors integrate both general-purpose CPU cores and specialized accelerators. Energy efficiency is the primary design goal for those processors, which has recently rekindled interest in neural network accelerators. Neural network accelerators trade the accuracy of computation for performance and energy efficiency and are suitable for errortolerant media applications such as video and audio processing. However, most existing accelerators only exploit inter-neuron parallelism and leave processing elements underutilized when the number of neurons in a layer is small. Thus, this paper proposes a novel neural network accelerator that can efficiently exploit both inter- and intra-neuron parallelism. For five applications the proposed accelerator achieves average speedups of 126% and 23% over a generalpurpose CPU and a state-of-the-art accelerator exploiting inter-neuron parallelism only, respectively. Besides, the proposed accelerator saves energy consumption by 22% over the state-of-the-art accelerator1. Index Terms — hardware accelerator, neural network, lowpower, scheduling.
I. INTRODUCTION Today’s mobile consumer electronics devices are required to execute a variety of applications such as web browsers, media players, games, and so on. These devices are, in effect, becoming a new class of general-purpose computers for which new applications are continuously updated and added throughout their lifetime. For example, some mobile devices, such as smartphones and tablets, already have thousands of applications available for installation. Many compelling applications have recently emerged to
This work was supported in part by the Ministry of Science, ICT & Future Planning (MSIP) under the IT R&D program (KI001810041244, Smart TV 2.0 Software Platform), and the Basic Science Research Program (NRF2014R1A1A1005894). Doo Young Kim is with Sungkyunkwan University (SKKU), Suwon, 440746, Republic of Korea (e-mail: dooyoungid@https://www.sodocs.net/doc/0215836965.html,). Jin Min Kim is with Samsung Electronics, Yongin, 446-711, Republic of Korea (e-mail: jinmin01.kim@https://www.sodocs.net/doc/0215836965.html,). Hakbeom Jang is with Sungkyunkwan University (SKKU), Suwon, 440746, Republic of Korea (e-mail: hakbeom@https://www.sodocs.net/doc/0215836965.html,). Jinkyu Jeong is with Sungkyunkwan University (SKKU), Suwon, 440-746, Republic of Korea (e-mail: jinkyu@https://www.sodocs.net/doc/0215836965.html,). Jae W. Lee is with Sungkyunkwan University (SKKU), Suwon, 440-746, Republic of Korea (e-mail: jaewlee@https://www.sodocs.net/doc/0215836965.html,). Contributed Paper Manuscript received 10/02/15 Current version published 12/29/15 Electronic version published 12/29/15.
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enhance user experience to an unprecedented level, such as image search [1], speech recognition [2], and so on. By autonomously perceiving the user’s needs, mobile devices can provide personalized, context-aware services that were not previously possible [3]. However, these emerging applications demand a large amount of computation, and it is very challenging to execute them efficiently on batterypowered mobile devices [4]. To deliver both high performance and energy efficiency, application-specific accelerators, along with general-purpose CPU cores, are commonly employed on mobile application processors [5]. Among them neural network accelerators have recently drawn much attention for their broad applicability and high efficiency [3], [4], [6]. Neural network accelerators effectively implement approximate functions for applications that can tolerate errors in the program output, thus trading the output quality for performance and energy efficiency. For example, video processing applications can tolerate a small number of errors (i.e., broken pixels) with little degradation of user experience. This kind of approximation [7]-[9] is applicable to other domains as well, such as image search [1], speech recognition [2], data search and mining [10]. Among a variety of neural network models, Multi-Layer Perception (MLP) [11] is one of the most popular ones for its applicability and flexibility. MLP is a feedforward artificial neural network and consists of multiple layers with varying numbers of neurons, where every pair of adjacent layers are fully connected. MLP is usually trained by a back-propagation algorithm [12], using the original function's input-output pairs only. However, most of the hardware MLP accelerators exploit only inter-neuron parallelism (or node parallelism), hence underutilizing hardware resources, especially when the number of neurons for a layer is smaller than the number of available processing elements [6]. To address this limitation, this paper proposes a novel hardware MLP accelerator that can exploit both inter- and intra-neuron parallelism. The proposed MLP accelerator allocates multiple processing elements to a single neuron if there are fewer neurons than the number of processing elements (PEs) for a given layer. With intelligent scheduling for executing neurons, the proposed accelerator achieves significantly higher resource utilization than a state-of-the-art MLP accelerator [6], hence yielding superior performance and energy efficiency. To demonstrate this, five programs are taken from various application domains of consumer electronics, including image compression, object recognition,
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Fig. 1. Image quality degradation with increasing bit error rate.
3D gaming, and robotics. Among them a Sobel edge detector is presented in greater detail as an application case study. II. BACKGROUND A. Approximate Computing for Energy Efficiency Human visual and auditory systems are known to be tolerant of errors in video and audio data. Many popular compression standards for media data (e.g., jpeg, mp3, h.264) are lossy in that they lose a small fraction of data bits to maximize compression ratio [13], [14]. Likewise, approximate computing trades the accuracy of computation primarily for reduction in the amount of computation, hence improving performance and energy efficiency while maintaining a “good enough” quality of the program output. This approach can be applied to non-media processing applications as well, such as speech recognition, face recognition, augmented reality, bigdata analytics, and so on [15]. Fig. 1 illustrates the degradation of image quality when a varying number of least significant bits (LSBs) (two, four, and six) in each 8-bit color component are set to zero. Each image is annotated with Peak Signal-to-Noise Ratio (PSNR) in decibel (dB). Even with four broken LSBs the image quality is still acceptable; only with 6 broken LSBs the image quality is noticeably degraded. Therefore, by applying approximation judiciously, it is feasible to reduce energy consumption greatly without degrading user experience (i.e., quality degradation is (almost) not perceivable by the user). This is particularly attractive on energy-constrained consumer electronics devices such as smartphones and wearable devices. Relaxing the overly restrictive correctness measure of program outcomes opens up opportunities for maximizing battery life and reducing operating temperature, hence improving user satisfaction. B. Multi-Layer Perception (MLP) Neural Networks To realize effective approximation, neural network accelerators have recently drawn much interest from the research community. A neural network is a system of interconnected neurons, which collectively approximates a function that would be expensive to calculate precisely. Each synapse, which connects a pair of neurons, has a weight that quantifies connection strength between them. A neural network is trained, typically using a fixed input set, to determine synaptic weights. While there are a number of different kinds of neural networks [7]-[9], [11], [16], Multi-Layer Perception (MLP) is
Fig. 2. Multi-Layer Perception (MLP) network with a 1-4-4-2 topology.
one of the most popular ones for its applicability and flexibility. Fig. 2 illustrates an MLP network with four layers—one input layer (I), two hidden layers (H1 and H2), and one output layer (O). All neurons between a pair of adjacent layers are fully connected. The number of neurons in the input and output layers is determined by the number of input and output parameters of the function being approximated. For example, the function being modeled in Fig. 2 takes one input and generates two outputs. The number of hidden layers and the number of neurons for each of them are configured in a training process. MLP networks are typically trained with a back-propagation algorithm [12] to adjust the synaptic weights of the network to minimize error rate (e.g., mean square error (MSE)). Once training is completed, output values are calculated by activating neurons from the input layer towards the output layer. Each neuron in the network first calculates a weighted sum on its inputs using synaptic weights, and then applies a sigmoid function (sigmoid(x) = 1/[1+e-x]) to the weighted sum. For example, the output from the second neuron in the second hidden layer (labeled “H2_1”) is calculated to be sigmoid(w0x0+w1x1+w2x2+w3x3), where wi is the synaptic weight for the incoming edge from neuron H1_i and xi is the output of the neuron. Since data dependences exist only between layers but not within a layer, all neurons in the same layer can be activated in parallel. This is called inter-neuron parallelism, or node parallelism. Fig. 3 illustrates an example schedule of the MLP network in Fig. 2 on a neural network accelerator with 8 processing elements (PEs). In the figure Hi_j denotes j-th neuron in hidden layer i, and O_j j-th neuron in the output layer. This schedule activates all neurons in a layer concurrently to exploit inter-neuron parallelism. Once execution of the layer is finished, the neurons broadcast their output values (labeled “Communication” in Fig. 3), which will be used as input values in the next layer. However, inter-neuron parallelism is generally not sufficient to fully utilize the available PEs when the number of neurons in a layer is smaller than that of PEs. Fig. 3 demonstrates that the MLP network in Fig. 2 utilizes at most 4

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Fig. 4. MLP schedule with both inter- and intra-neuron parallelism.
Fig. 3. MLP schedule with inter-neuron parallelism only.
PEs because all layers have 4 or fewer neurons. This resource underutilization problem will likely be more pronounced in the future with an increasing number of PEs on a chip. To fully utilize PEs, it is highly desirable to exploit intraneuron parallelism as well as inter-neuron parallelism. If the number of neurons is smaller than the number of PEs as in Fig. 3, the scheduler may allocate more than one PEs for one neuron. In this case each PE is responsible for calculating a weighted sum for a disjoint subset of the inputs, which will be merged into a single weighted sum. However, most of the existing neural network accelerators exploit only inter-neuron parallelism. Therefore, this paper introduces a novel MLP network accelerator, which effectively exploits both inter- and intra-neuron parallelism. III. MLP ACCELERATOR DESIGN This section presents the design and implementation of an MLP neural network accelerator that can efficiently exploit both inter- and intra-neuron parallelism. It aims to maximize resource utilization, hence minimizing idling time in PEs. A. Execution Model Fig. 4 shows an execution schedule for the neural network in Fig. 2 (with a 1-4-4-2 topology) on the proposed MLP network accelerator. It alternates between computation and communication phases until the output is obtained. Computation phases include calculation of weighted sums and sigmoid function (shown by shaded boxes). In communication
phases PEs send and receive data via a shared bus (shown by white boxes). A communication box in Fig. 4 is labeled with the identifier of data being transferred. Whenever there are more PEs available than the number of neurons in a layer, the accelerator allocates multiple PEs to each neuron to exploit intra-neuron parallelism. This is different from the resource allocation strategy of a state-ofthe-art MLP accelerator [6], where each neuron is allocated only one PE. For example, there are four neurons in H2 layer (H2_0 through H2_3), and each neuron is allocated two PEs to calculate its weighted sum. PE0 calculates a partial weighted sum for the first two inputs from H1_0 and H1_1, and PE1 for the last two inputs from H1_2 and H1_3. Once partial weighted sums are obtained, PE1 sends the partial sum to PE0 identified with a label of H2_(0,1), where the three numbers indicate layer number, neuron number, and local PE
Fig. 5. Hardware organization of the proposed accelerator.

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TABLE I COMMAND ENCODINGS IN WEIGHT BUFFER 3-bit Encoding 000 100 101 110 (merge) 111 (merge) Command Weighted-sum execution only Weighted-sum passes through sigmoid unit and is written to output buffer Weighted-sum bypasses sigmoid unit and is written to output buffer Partial weighted-sums are merged from neighboring PEs, and the result is written to output buffer after sigmoid Partial weighted-sums are merged from neighboring PEs, and the result is written to output buffer without applying sigmoid
IEEE Transactions on Consumer Electronics, Vol. 61, No. 4, November 2015
identifier, respectively. The PE identifier is local within a neuron and starts with zero. In case of layer H2, each neuron has two PEs whose local PE identifiers are 0 and 1, respectively. Then the two partial sums are merged at PE0 to which a sigmoid function is applied to obtain the final output for neuron H2_0. As long as each neuron has enough work to do to amortize the cost of merging, the proposed accelerator achieves higher resource utilization and hence performance. B. Hardware Organization Fig. 5(a) shows the organization of the proposed accelerator, which is composed of eight PEs, input FIFO, configuration FIFO, output FIFO, scheduler and scaling unit. Each PE communicates with the other PEs and FIFOs through a shared bus. To provide efficient pairwise communication for merging operations, the shared bus can be divided into multiple segments on demand, possibly using tri-state gates. This allows up to four neurons to transfer intermediate data concurrently through the segmented bus. The scheduler orchestrates communication among bus masters and slaves. More specifically, the scheduler controls bus transfers to send input values from the input FIFO to destination PEs, weight values from the configuration FIFO to destination PEs, and intermediate results from one PE to another. The scaling unit is used to normalize the input and output values. The internal organization of each PE is shown Fig. 5(b). The fused multiply-adder (FMA) multiplies an input value by a weight and accumulates the product using an accumulator register. Once the accumulation process is completed, the result is either sent to a higher-order local PE (if it is a partial weighted sum), or fed into the sigmoid function (if it is a final weighted sum for the neuron). The controller determines whether the PE accumulates the products or merges the weighted sums from neighboring PEs, based on a 3-bit command associated with each entry in the weight buffer as shown in TABLE I. C. Scheduler Operations Communication between PEs and FIFOs are statically scheduled. The bus scheduler in the accelerator (Fig. 5(a)) orchestrates bus transactions between masters and slaves. The training process produces not only a topology and synaptic weights but also a bus schedule as well. This information is loaded into the scheduler through configuration FIFO during an initialization phase.
Fig. 6. MLP schedule with both inter- and intra-neuron parallelism in a 216-4-2 topology.
Fig. 6 shows an execution schedule of Inversek2j, a robotics application, with a 2-16-4-2 topology on the proposed accelerator with 8 PEs. More details about the application are available in Section IV. The first hidden layer (H1) has enough number of neurons, and inter-neuron parallelism is sufficient to fully utilize the PEs. However, the second hidden
TABLE II BUS TRANSACTION SCHEDULE BETWEEN H1 AND H2 FOR INVERSEK2J SENDER (H1 – 16 NEURONS) NEURON 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 H1_0 H1_1 H1_2 H1_3 H1_4 H1_5 H1_6 H1_7 H1_8 H1_9 H1_10 H1_11 H1_12 H1_13 H1_14 H1_15 PE 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 RECEIVERS (H2 – 4 NEURONS) (NEURON, LOCALID) H2_(*, 0) H2_(*, 0) H2_(*, 0) H2_(*, 0) H2_(*, 0) H2_(*, 0) H2_(*, 0) H2_(*, 0) H2_(*, 1) H2_(*, 1) H2_(*, 1) H2_(*, 1) H2_(*, 1) H2_(*, 1) H2_(*, 1) H2_(*, 1) PE 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 1, 3, 5, 7 1, 3, 5, 7 1, 3, 5, 7 1, 3, 5, 7 1, 3, 5, 7 1, 3, 5, 7 1, 3, 5, 7 1, 3, 5, 7
STEP

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Fig. 7. MLP schedule with both inter- and intra-neuron parallelism in a 2-16-4-2 topology.
layer (H2) has only four neurons; thus, intra-neuron parallelism is exploited as well, to improve resource utilization. It is also applied to the output layer (O). TABLE II shows a bus transaction schedule between two hidden layers (H1 and H2). The outputs from H1 neurons are broadcast to H2 neurons over 16 transactions. Since a neuron in H2 layer is allocated two PEs, one PE (with LocalID=0) receives the first half of the outputs from H1, and the other PE (with LocalID=1) the second half. Fig. 7 shows an execution schedule when the number of PEs increases to 16. Algorithm 1 presents a pseudo code that finds a neuron-toPE mapping at a given layer. The algorithm returns a range of PE IDs (from peidmin to peidmax, inclusive) allocated to the given neuron whose ID is nid. If the number of neurons (N) in this layer is divisible by the number of PEs (P), only interneuron parallelism will be exploited to fully utilize the PEs [6]. The first hidden layer (H1) of inversek2j in Fig. 6 is such an example with N equal to 16. If N is not divisible by P, the number of residual neurons (R) is not zero, and intra-neuron parallelism may be exploited when executing them. Fig. 8 demonstrates such an example with a 1-8-9-2 topology. The second hidden layer (H2) has 9 neurons, which is not a multiple of P. During the first round of execution 8 PEs are allocated to 8 neurons (H2_0 through H2_7) to exploit inter-neuron parallelism only. During the second (last) round there is only one residual neuron (i.e.,
H2_8), which exploits only intra-neuron parallelism to use all 8 PEs to calculate partial sums in parallel. Fig. 9 shows another example of exploiting intra-neuron parallelism with a 1-8-3-2 topology. The second hidden layer (H2) has only three neurons, which does not divide the Algorithm 1. Finding a neuron-to-PE mapping Input: P (Number of PEs), N (Number of neurons in this layer), nid (Neuron’s ID, 0 ≤ nid < N) Output: peidmin, peidmax (a range of PE IDs allocated to the neuron, 0 ≤ peidmin ≤ peidmax < P) Q = N / P; // number of rounds with inter-neuron parallelism R = N mod P; // number of residual neurons if ( nid < Q * P ) // exploiting inter-neuron parallelism only (1 PE/neuron) peidmin = peidmax = nid mod P; else // exploiting intra-neuron parallelism (≥ 1 PEs/neuron) PEsPerNeuron = P / R; peidmin = (nid mod P) * PEsPerNeuron; peidmax = peidmin + (PEsPerNeuron - 1); endif

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Fig. 9. MLP schedule with both inter- and intra-neuron parallelism in a 18-3-2 topology.
Fig. 8. MLP schedule with both inter- and intra-neuron parallelism in a 18-9-2 topology.
number of PEs (P=8). In this case only two PEs are allocated to each neuron, and the remaining two PEs are left idle. As each neuron is required to calculate the sum of eight products by taking the outputs from H1_0 through H1_7, a PE calculates four products per each. Note that exploiting intraneuron parallelism comes with a cost of merging. In this case, a single merge step combines the results from two PEs (i.e., adds two partial sums) for each neuron. In general, if a neuron is executed over Pintra PEs, the computation time is reduced by a factor of Pintra at the cost of merging proportional to log2Pintra. A quantitative analysis in Section IV demonstrates that exploiting intra-neuron parallelism pays off in terms of both performance and energy efficiency. D. CPU Interface In typical use cases functions that can be approximated in an application are offloaded to the proposed MLP accelerator. Therefore, the host CPU must have an interface to control the operation of the accelerator and transfer data to and from it. As presented in Section 3.B, the accelerator exposes three
FIFOs for communication with the CPU. To access theses FIFOs, the instruction set architecture (ISA) of the CPU is extended with three new instructions: (1) put.data($reg) to enqueue the value of $reg to the input FIFO; (2) get.data($reg) to dequeue a data element from the output FIFO to $reg; (3) put.config($reg) to enqueue the value of $reg to the config FIFO. The instructions are summarized in TABLE III. Using these three instructions, the hardware accelerator can be configured, and can execute the function with given inputs. Typically, the topology of the neural network, including the number of neurons for each layer and synaptic weights, is encoded and communicated to the accelerator with multiple invocations of put.config($reg) instruction. In the setup of this paper, the topology is determined by an offline learning algorithm based on back propagation [12]. Then the CPU sends input data by invoking put.data($reg) instructions to commence function execution. Finally, return values are read from the output FIFO by the CPU using get.data($reg) instructions. Note that all three instructions in Table III are blocking; put (get) instructions will be blocked if the FIFO is full (empty).
TABLE III ISA EXTENSIONS Instruction put.data($reg) get.data($reg) put.config($reg) Descriptions Enqueue the value of $reg to input FIFO Dequeue a data element from output FIFO Enqueue the value of $reg to configuration FIFO

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TABLE IV APPLICATION LIST Application Blackscholes Jpeg Sobel Jmeint Inversek2j Descriptions Predicts the price of options JPEG encoding Sobel edge detector Triangle intersection detection Inverse kinematics for 2-joint arm TABLE V TRAINING RESULTS Application Blackscholes Jpeg Sobel Jmeint Inversek2j Topology 6-32-2-1 64-32-64 9-16-1 18-8-4-1 2-16-4-2 Error metric Fraction of prediction errors Average relative error Average relative error Misclassification rate Average relative error Error 9.57% 6.89% 7.07% 7.04% 5.08% Domain Financial market prediction Compression Image processing 3D gaming Robotics
IV. EVALUATION A. Methodology To train the neural network (i.e., to determine topology and synaptic weights) a back-propagation algorithm taken from Fast Artificial Neural Network (FANN) library [17] is used. This training procedure is performed offline for each application. For fair comparison a separate training set of the input is used for training; another test set is used for evaluation. The unrestricted topology space is too large, so this work limits the number of hidden layers to up to two and the number of neurons per hidden layer to power of two with a maximum of 32, following the common methodology of a state-of-the-art MLP accelerator [6]. With these limitations, the number of possible topologies is reduced to 30. Note that these limitations are imposed just to keep the training time manageable, and that there are no fundamental limitations that prevent the proposed accelerator from accommodating more complex topologies—for example, with more than two hidden layers, an odd number of neurons per layer, and so on. If the number of PEs are greater than the number of neurons, PEs are fairly distributed to all neurons in a layer (e.g., 2 PEs/neuron if there are 8 PEs and the layer in question has 4 neurons); if there are fewer PEs than the number of neurons, it takes multiple iterations to calculate the results of the layer, and only the last iteration exploits intraneuron parallelism (if exists). The cycle-level performance model of the proposed accelerator builds on an open-source processor simulator [18]. The CPU model is based on the x86 ISA with 32KB L1 instruction cache, 32KB L1 data cache, and 2MB unified L2 cache. To estimate the area and power consumption of the accelerator, a Register-Transfer Level (RTL) Verilog model is implemented and synthesized using a 45nm standard cell library [19]. Five applications are selected for evaluation as summarized in TABLE IV [6]: Blackscholes, Jpeg, Sobel, Jmeint, and Inversek2j. These applications satisfy the following three requirements for approximation. First, they have at least one hot function that can be approximated. Second, the output of the program can tolerate a small degree of quality degradation. Third, the inputs and outputs are well defined such that a fixed input always produces the same output deterministically. For evaluation the results from the functions offloaded to the accelerator (instead of the entire program) are gathered and reported as the portion of approximable regions can vary widely across applications. B. Training Results TABLE V summarizes the results of training using the FANN library. The topology is obtained using a training set of the input, and the error rate is measured using a test set of the input. Error rates are measured using different metrics depending on the applications as discussed below. Blackscholes is a mathematical model to predict the financial market. This algorithm includes a function that solves a differential equation estimating an option price over
time, which is approximated. The error rate is measured by the fraction of estimated prices that deviate from the real prices beyond a certain threshold. Jpeg is a widely used image compression algorithm. Functions for discrete cosine transform and quantization are approximated. The error metric is a relative error of pixel values averaged over all RGB components in an image. Sobel filter is used to detect edges in an input image. It uses 3x3 matrix convolution to estimate the image’s intensity gradient, which is approximated. As it generates a filtered output image, the error metric is average relative error, which is the same as Jpeg. Jmeint is a commonly used algorithm for 3D gaming. This algorithm detects an intersection between a pair of 3D triangles to produce one-bit output. Therefore, the error metric is misclassification rate. Inversek2j is a robotics application, which produces numeric outputs, so average relative error is used as error metric. Overall, the trained neural network produces the output of an acceptable quality with an average error rate of 7.13% with a maximum error rate of 9.57% for Blackscholes. The reported error rates are comparable with other related work [6]. C. Performance, Area, and Energy Consumption Fig. 10 shows performance speedups normalized to CPUonly execution of the original, precise version of the function. Esmaeilzadeh et al [6] represent a state-of-the-art neural network accelerator that exploits inter-neuron parallelism only, to allocate one processing element (PE) for each neuron. For
Fig. 10. Execution time evaluation of hardware accelerator

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V. RELATED WORK Recently, techniques to reduce energy consumption via approximation have been actively investigated, as energy efficiency becomes the primary design goal for all scales of computing systems, including consumer electronics devices. These techniques can be categorized into hardware-based techniques and software-only techniques. Several techniques require hardware modifications to support approximation [6], [15], [21]. Truffle [21] is a processor microarchitecture that exploits dual-voltage operations, with high voltage for precise operations and low voltage for approximate operations. EnerJ [15] extends a Java type system to support both precise and approximate variables, targeting an approximable microarchitecture like Truffle. Then the compiler automatically generates code that maps approximate variables to approximate storage and operations. These approaches significantly increase the complexity of hardware, and hence design and verification cost, as the datapath and control logic have to maintain both correct and approximate versions. Esmaeilzadeh et al [6] propose a standalone neural processing unit (NPU), which effectively offloads an approximable function from the CPU to achieve higher performance and energy efficiency. The programmer first identifies approximable code regions, and the function input is communicated to an NPU exploiting ISA extensions. The NPU design is based on the MLP neural network model. However, the NPU exploits only inter-neuron parallelism (but not intra-neuron parallelism) to underutilize hardware resources as demonstrated in Section IV. Alternatively, there are software-only approaches to approximate computing that do not require any hardware modifications [22]. Typically, there are multiple versions of a function with different quality-efficiency tradeoffs, and the runtime system chooses an optimal version (e.g., with minimal energy consumption) while satisfying the user-specified quality goal. However, they often require manual efforts to produce an approximate code or annotate their code using language extensions for each application. To reduce the programmer’s burden, compiler-based approximation techniques [23]-[25] exploit compiler support to generate multiple versions of a function and find an optimal version during execution. Agarwal et al [24] propose code perforation by discarding loop iterations to improve performance and energy consumption. SAGE [23] accelerates graphic programs on GPUs by choosing the multiple approximate kernels at the runtime. However, these (almost) automated software-only techniques have limited applicability and often produce the output of an unacceptable quality. VI. CONCLUSION This paper proposes a novel neural network accelerator based on Multi-Layer Perception (MLP) that can efficiently exploit both inter- and intra-neuron parallelism. Evaluation with five error-tolerant applications in various domains
Fig. 11. Application example of the proposed MLP accelerator for Sobel edge detection.
the five applications the proposed accelerator achieves an average speedup of 126% over CPU-only execution and 23% over the state-of-the-art accelerator. Speedups over the stateof-the-art are higher for those applications with layers that cannot fully exploit PEs (i.e., number of neurons in a layer is either small or not divisible by PE count). However, no speedup is achieved for Jpeg as both accelerators have the same neuron-to-PE allocation due to a 64-32-64 topology. According to synthesis results using a Verilog RTL model of the proposed accelerator targeting a 45nm technology, it achieves energy savings of 22% on average (calculated by a product of estimated power and execution time) while incurring only about 9% area overhead compared to the stateof-the-art accelerator. D. Application Case Study: Sobel Filter for Edge Detection Sobel filter [20] is one of the most widely used edge detection algorithms to enable many interactive, media-rich applications such as augmented reality, object recognition, and image search. These applications are both computeintensive and tolerant of bit errors to make excellent targets for neural acceleration [6]. Fig. 11 shows the results of applying two versions of Sobel filters to the original image in Fig. 11(a). Fig. 11(b) shows the output from the precise Sobel filter, whereas Fig. 11(c) the output from the proposed neural network accelerator. Their difference is hardly detectable by human eyes with an average error rate of only 7.07%. While maintaining acceptable quality, the proposed accelerator reduces execution time by 77.6% and 33.1%, compared to the baseline CPU and the state-of-the-art MLP accelerator [6], respectively. This accelerator can be used to enable real-time augmented reality applications on energy-constrained mobile devices, for example.

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including image processing, compression, financial option pricing, and robotics, the proposed accelerator achieves average speedups of 126% and 23% over CPU and a state-ofthe-art MLP accelerator exploiting inter-neuron parallelism only, respectively. Also, the proposed accelerator provides energy-savings of 22% with area overhead of only 9% compared to the state-of-the-art accelerator. REFERENCES
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Hakbeom Jang received his B.S. degree in Computer Engineering from Sunghyunkwan University (SKKU) in 2011, and an M.S. degree in Electrical and Computer Engineering from the same university in 2014. He is currently a Ph.D. candidate in the Department of Electrical and Computer Engineering at SKKU. His current research interests include multi-core systems, memory systems, and mobile systems. Jinkyu Jeong received his B.S. degree in Computer Science from Yonsei University and Ph.D. degree from Korea Advanced Institute of Science and Technology (KAIST) in 2013. He is currently an assistant professor in the Department of Semiconductor Systems Engineering at Sungkyunkwan University (SKKU). His research interests include real-time systems, operating systems, virtualization, and embedded systems. Jae W. Lee (S’98-M’09) received his B.S. degree in Electrical Engineering from Seoul National University, M.S. degree in Electrical Engineering from Stanford University, and Ph.D. degree in Computer Science from Massachusetts Institute of Technology (MIT) in 2009. He is currently an assistant professor in the Department of Semiconductor Systems Engineering at Sungkyunkwan University (SKKU), Korea. His research areas include computer architecture, VLSI design, compilers, parallel programming, and computer security.
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非晶合金、纳米晶薄带项目

非晶合金、纳米晶薄带项目可行性研究报告

第一章项目概况 第一节基本情况 一、项目名称:非晶合金、纳米晶薄带生产 二、承办单位:****有限公司 三、企业性质:有限责任公司 四、企业法人:***** 五、项目建设地点:******* 第二节项目产品描述 非晶合金薄带是70年代问世的一种新型软磁材料,它采用先进的速凝固技术,把熔化的钢液以1×106℃/S的冷却速度直接冷却成厚度仅为20um—40um的金属薄带,与传统金属带材生产工艺相比,节省了五~六道工序。生产过程节能,无污染排放。由于采取了超急冷却技术,带材中原子排列组合上具有短程有序,长程无序特点的非晶合金组织。该合金具有许多独特性能特点:如优异的磁性,耐蚀性,耐磨性,高硬度,高电阻率等,被人们称为二十一世纪最新的绿色环保软磁材料。 该材料的应用范围广阔,可替代传统的硅钢,铁氧体和坡莫合金等软磁材料,用该材料作为铁芯主要用材并制造的非晶合金配电变压器,与用硅钢片作为铁芯的配电变压器比对,具有很好的节能效果。其比对效果见下表:

由上表可见,平均空载损耗降低70%~80%,其节能效果显著. 第三节项目背景 目前,全球只有日立金属大规模生产非晶合金带材。日立金属的非晶合金带材的产能,于07年扩张至5.2万吨后,理论上,也只能生产出3058万kV A非晶合金变压器,以上产量与我国目前每年约2.4亿kV A配电变压器的需求量相距甚远。而我国的非晶合金带材主要依赖于进口,因此,非晶合金带材的供给,成为我国大规模推广应用非晶合金变压器的最大障碍。 我国非晶合金变压器的研制工作始于“七五”,掌握非晶合金变压器生产技术的企业较多。国家80年代科技攻关课题中,将“非晶合金铁芯配电变压器研制”作为重点课题。1986年5月,上海钢铁研究所与宁波变压器厂合作,用该所研制的非晶合金带材试制出国内第一台单相3kV A非晶合金变压器。目前,除上海置信电气以外,我国其它知名变压器生产企业,如顺特电气、江苏华鹏、特变电工、杭州钱江电器集团、天威保变、西变等厂家均掌握了非晶合金变压器的生产技术。但是,由于非晶合金带材的供应依赖于进口,加之受到带材出口国的制约和价格上涨的因素影响,实际上以上厂家的非晶合金变压器均未大规模生产。铁芯及变压器的生产技术并不是制约我国推广非晶合金变压器的关键性因素,如原材料供应问题得到缓和,变压器生产厂家要扩大非晶合金变压器产能易如反掌,只有非晶合金带材生产的国产化才能促成非晶合金变压器规模化生产的飞跃。目前,日立金属

非晶和纳米晶合金的比较

铁基非晶合金在工频和中频领域,正在和硅钢竞争。铁基非晶合金和硅钢相比,有以下优缺点。 1)铁基非晶合金的饱和磁通密度Bs比硅钢低 但是,在同样的Bm下,铁基非晶合金的损耗比0.23mm厚的3%硅钢小。一般人认为损耗小的原因是铁基非晶合金带材厚度薄,电阻率高。这只是一个方面,更主要的原因是铁基非晶合金是非晶态,原子排列是随机的,不存在原子定向排列产生的磁晶各向异性,也不存在产生局部变形和成分偏移的晶粒边界。因此,妨碍畴壁运动和磁矩转动的能量壁垒非常小,具有前所未有的软磁性,所以磁导率高,矫顽力小,损耗低。 2)铁基非晶合金磁芯填充系数为0.84~0.86 3)铁基非晶合金磁芯的工作磁通密度 1.35T~1.40T,硅钢为1.6T~1.7T。铁基非晶合金工频变压器的重量是硅钢工频变压器的重量的130%左右。但是,即使重量重,对同样容量的工频变压器,磁芯采用铁基非晶合金的损耗,比采用硅钢的要低70%~80%。 4)考虑损耗,总的评估价为89% 假定工频变压器的负载损耗(铜损)都一样,负载率也都是50%。那么,要使硅钢工频变压器的铁损和铁基非晶合金工频变压器的一样,则硅钢变压器的重量是铁基非晶合金变压器的1?8倍。因此,国内一般人所认同的抛开变压器的损耗水平,笼统地谈论铁基非晶合金工频变压器的重量、成本和价格,是硅钢工频变压器的130%~150%,并不符合市场要求的性能价格比原则。国外提 出两种比较的方法,一种是在同样损耗的条件下,求出两种工频变压器所用的铜铁材料重量和价格,进行比较。另一种方法是对铁基非晶合金工频变压器的损耗降低瓦数,折合成货币进行补偿。每瓦空载损耗折合成5~11美元,相当于人民币42~92元。每瓦负载损耗折合成0.7~1.0美元,相当于人民币6~8.3元。例如一个50Hz,5kVA单相变压器用硅钢磁芯,报价为1700元/台;空载损耗28W,按60元人民币/W计,为1680元;负载损耗110W,按8元人民币/W计,为880元;则,总的评估价为4260元/台。用铁基非晶合金磁芯,报价为2500元/台;空载损耗6W,折合成人民币360元;负载损耗110W,折合成人民币880元,总的评估价为3740元/台。如果不考虑损耗,单计算报价,5kVA铁基非晶合金工 频变压器为硅钢工频变压器的147%。如果考虑损耗,总的评估价为89%。 5)铁基非晶合金抗电源波形畸变能力比硅钢强 现在测试工频电源变压器磁芯材料损耗,是在畸变小于2%的正弦波电压下进行的。而实际的工频电网畸变为5%。在这种情况下,铁基非晶合金损耗增加到106%,硅钢损耗增加到123%。如果在高次谐波大,畸变为75%的条件下(例如工频整流变压器),铁基非晶合金损耗增加到160%,硅钢损耗增加到300%以上。说明铁基非晶合金抗电源波形畸变能力比硅钢强。 6)铁基非晶合金的磁致伸缩系数大 是硅钢的3~5倍。因此,铁基非晶合金工频变压器的噪声为硅钢工频变压器噪声的120%,要大3~5dB。

铁基非晶及纳米晶合金纤维的研制

*电子科技大学青年科技基金重点项目 铁基非晶及纳米晶合金纤维的研制 * 李 强,梁迪飞,鄢 波,邓龙江 (电子科技大学微电子与固体电子学院,成都610054) 摘要 通过自主开发的熔融快淬炉制备出了铁基非晶合金纤维,研究了制备工艺参数对纤维几何尺寸、微观形貌的影响,结果表明:转轮线速度、线圈功率(熔体温度)及气氛等对其微观形貌和几何尺寸的影响较大,通过调整优化 工艺参数可稳定地制备直径为10~40μm 可调的非晶磁性纤维。通过适当热处理可得到双相纳米晶磁性合金纤维。 关键词 铁基非晶合金 非晶合金纤维 熔融快淬 The Fabrication of Fe -base Amorphous and Nanocrystalline Alloy Microwires LI Qiang ,LIANG Difei ,YAN Bo ,DENG Long jiang (Scho ol of M ic roelect ronic and Solid -state Electro nics ,U ES T C ,Chengdu 610054) A bstract T he microw ires o f Fe -base amo rphous alloy hav e been fabrica ted with the equipment deve loped by us.T he rela tionships between the fabrica tion pr ocess and micr owire dimensions ,mor pho log y have also been inv estiga -ted.A s a re sult ,the main facto r s im pact the micro wire dimensions ,mor pho log y are the w heel velocity ,pow er of the lo op (temperature o f the melting )and ambience.T he diameter s o f the micro wires could be within 10~40μm.By sub -sequent annealing ,nanocry stralline micr owire s can be obtained. Key words F e -ba se amo rpho us alloy ,amo rphous a llo y microw ir es ,melt quench   0 前言 自1988年Yoshizawa 等[1,2]首次报道具有优异软磁性能的 Finemet 型F e 基合金以来,对非晶及纳米晶合金材料的研究和应用越来越广,但多为对粉体和薄带的研究,而对于非晶及纳米晶合金纤维的制备和特性的研究,特别是国内在这方面的研究则相对更少。 近几年国内外所研究的非晶合金纤维一般多采用玻璃包覆熔纺法制备[3],它是根据液态玻璃粘度高易于制成纤维的原理,把金属棒插入玻璃管中作原料,在其下端设置一个高频感应线圈,原料通过感应线圈被逐渐加热熔化,熔化了的玻璃包覆着液态金属经急速冷却后制得圆而长的细丝。金属纤维的直径为1~100μm ,表面约有500~2000nm 厚的微细多晶层。由于玻璃的导热性较差,所以不管用何种冷却介质都会影响熔融合金的冷却速度,故此法只适用于临界冷却速率较低的非晶合金纤维的制备。 另外一种方法是熔融快淬法[4,5],其基本原理是:熔融态合金液面接触到高速旋转的尖锐的高导热轮缘,快速固化形成完全非晶的合金纤维,通过剥离装置使之脱离轮缘。由于此法大大提高了冷却速率,所以可快淬具有较高熔点的材料,如铁基材料等,而且所制备的非晶纤维具有很好的表面光洁度和粗细均匀度。本文即采用此方法制备非晶纤维样品。 1 实验 1.1 试验方法及样品制备 使用的试验设备如图1所示。在可密闭的箱体中,利用高频感应线圈将耐热石英玻璃管中成分为F eCuN bSiB 的合金块材熔化。熔化后的合金由于表面张力的原因而呈馒头状凸起,利用进料装置使石英管内熔融合金液体在石英棒塞的挤压下平稳缓慢上升,使其液面与高速旋转的通有冷却水的铜轮的辊面接触,接触后液态金属即被快淬甩出。设置适当的进料速度、高频感应线圈功率(即熔融合金的温度)及铜轮线速度即可制备出粗细均匀、直径可控制在10~40μm 范围内的铁基非晶合金磁性纤维。 图1 试验设备简图 由于冷却的铜轮侧周为呈一定角度的尖锐轮缘(如图2所示),熔融合金因其表面附着力而立即被旋转的铜轮辊面尖角抽出,经铜轮以105~106℃/s 快淬后即呈纤维状,并在离心力和

非晶合金COFeNbSiB的纳米晶化及磁性

非晶合金COFeNbSiB的纳米晶化及磁性 作者:赵玉华, 何开元, 张雅静, 赵恒和, 张玉梅, 王建保, 程力智 作者单位:东北师范大学 刊名: 材料研究学报 英文刊名:CHINESE JOURNAL OF MATERIALS RESEARCH 年,卷(期):2001,15(2) 被引用次数:9次 参考文献(10条) 1.A Serebryakov;V Stelmukh;A Gurov查看详情 1995(04) 2.A Serebryakov;L Voropaeva;Yu Levin查看详情 1994(07) 3.赵玉华;何开元;赵恒和;张玉梅 李国纲 程力智Fe-Ni-Mo-(Si)-B非晶的晶化及纳米晶合金磁性的研究[期刊论文]-金属学报 2000(03) 4.Y Yoshizawa;K Yamauchi查看详情 1991 5.R.M.Bozorth;Ferro-magnetism查看详情 1951 6.M L Sui;F Zhou;K Y He;R.Wang L.Z.Cheng查看详情 1994(06) 7.S L He;K Y He;Z Wang查看详情 1997(06) 8.S L He;K Y He;B G Shen查看详情 1999(11) 9.A Serebryakov;V Sedykh;V Stelmukh查看详情 1996(05) 10.Y Yoshizawa;S Oguma;K Yamauchi查看详情 1988(64) 引证文献(9条) 1.万珍珍.朱正吼.李塘华FeCuNbSiB/丁基橡胶复合薄膜压磁性能的研究[期刊论文]-功能材料 2008(9) 2.李同.严彪.龙玲.杨沙.陈伯渠用于制备贴片电感的铁基非晶软磁合金的晶化过程研究[期刊论文]-金属功能材料 2008(2) 3.王冰霞Co基非晶/纳米晶的晶化及磁性能的研究评述[期刊论文]-金属功能材料 2007(2) 4.倪道情.黄庆丰医用钛及钛合金表面处理技术现状[期刊论文]-口腔材料器械杂志 2006(2) 5.支起铮.董帮少.陈文智.连法增Co51Fe18Nb6Si15B10纳米晶合金磁导率与温度的关系[期刊论文]-东北大学学报(自然科学版) 2006(2) 6.王姝Co基非晶软磁合金的磁性和结构的研究[学位论文]硕士 2005 7.郭红.晁月盛低频脉冲磁场致非晶合金Fe78Si9B13纳米晶化及机制[期刊论文]-机械工程材料 2004(3) 8.陈学定.宋翀旸.俞伟元.胡勇非晶软磁合金Fe73.5 Cu1Nb3Si13.5 B9的退火处理与性能研究[期刊论文]-兰州理工大学学报 2004(1) 9.宋翀旸.陈学定.俞伟元.蒋会荣Fe基非晶软磁合金的纳米晶化及磁性[期刊论文]-甘肃工业大学学报 2003(2) 本文链接:https://www.sodocs.net/doc/0215836965.html,/Periodical_clyjxb200102017.aspx

非晶纳米晶软磁材料

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和纳米尺度区域。在微观尺度区域,粒度和H c之间的反比关系(Hc-D-1)表示传统的原则,即大晶粒尺寸利于软磁性能的提高,但是大的晶粒和磁畴尺寸会增加铁损。在纳米尺度区域,新的非晶微晶合金落在常规的硅钢和铁基非晶合金之间。矫顽力和晶粒尺寸(Hc-D 6)关系显示,在纳米级别,晶粒尺寸的变化,即使是少量仍可能对最终的软磁特性产生显著影响[3,20]。 目前研究的Fe 基纳米晶软磁合金带材主要有Fe-Si-B 系、Fe-Zr-B 系和Fe-B 系。具体讲主要有三种牌号,分别是牌号为Finemet 的Fe-M-Si-Cu-B(M=Nb、Cr、V、W、Mo 等)合金,牌号为Nanoperm的Fe-M-B(M=Zr、Hf、Nb、Ta等)合金[5-6]和牌号为Hitperm的(Fe,Co)-M-B(M=Zr、Hf、Nb 等)合金[4-5]。三种牌号的合金都是采用对非晶合金前驱体进行晶化处理得到纳米晶合金的方法制备而成[1]。通过晶化退火处理不但可以有效地消除合金的内应力,还可以获得纳米晶结构的合金材料,因其具有超细化的显微组织从而表现出极佳的软磁性能[6]。 不同成分对铁基非晶纳米晶软磁性能有很大影响,本文目的是阐明对微观结构和软磁性能有充分研究的元素,如硅,硼,铜,铌,锆,氮掺杂,磷,镍,钴,氢化和锗对铁基非晶纳米晶合金特性的影响。表1总结了各成分的影响结果。 表1.Fe非晶/纳米晶合金添加元素的影响 2.合金元素的影响 2.1 Si和B Fe基合金的GFA比非铁合金系如Mg,Zr,Pd基合金低得多。事实上,通过铜模铸造在Zr和Pd基合金中可获得厚度大于1mm的块状金属玻璃,而在Fe基合金中形成的带材厚度只有几微米。添加B和Si可促进合金凝固过程中非晶态结构的形成,并且B对GFA的提高效应是Si的5倍[8]。此外,应当注意,尽管B可以增强GFA,但它也可以减少一次和二次结晶峰之间的安全间隙,如图2所示。这种物

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非晶合金纳米晶薄带生产建设项目 可行性研究报告 第一章项目概况 (3) 第一节基本情况 (3) 第二节项目产品描述 (3) 由上表可见,平均空载损耗降低70%?80%,其节能效果显著.5 第三节项目背景 (5) 第二章企业基本情况 (7) 第三章产品需求分析和改造的必要性 (9) 第一节项目建设的必要性 (9) 第二节市场需求分析 (10) 第四章改造的主要内容和目标 (11) 第一节厂址选择和建设条件 (11) 第二节生产规模 (13)

第三节工艺技术方案 (13) 第四节工程方案 (17) 第五节节能 (20) 第六节环境保护与劳动安全与工业卫生 (21) 第五章项目总投资、资金来源和资金构成 (25) 第六章人员培训及技术来源 (26) 第七章项目实施进度计划 (27) 第八章公司发展战略与市场营销计划 (28) 第九章项目经济效益和社会效益分析 (28) 第一节社会效益 (28) 第二节经济效益 (29) 第十章开发项目的技术经济分析 (31) 第一节风险分析 (31) 第二节风险对策 (32) 第一章概况 第一节基本情况 一、项目名称:非晶合金、纳米晶薄带生产 二、承办单位:**有限公司 三、企业性质:有限责任公司

四、企业法人: 五、项目建设地点: 第二节项目产品描述 非晶合金薄带是70年代问世的一种新型软磁材料,它采用先进的速凝固技术,把熔化的钢液以1X06C/S的冷却速度直接冷却成厚度仅为 20um—40um的金属薄带,与传统金属带材生产工艺相比,节省了五?六道工序。生产过程节能,无污染排放。由于采取了超急冷却技术,带材中原子排列组合上具有短程有序,长程无序特点的非晶合金组织。该合金具有许多独特性能特点:如优异的磁性,耐蚀性,耐磨性,高硬度,高电阻率等,被人们称为二^一世纪最新的绿色环保软磁材料。 该材料的应用范围广阔,可替代传统的硅钢,铁氧体和坡莫合金等软磁材料,用该材料作为铁芯主要用材并制造的非晶合金配电变压器,与用硅钢片作为铁芯的配电变压器比对,具有很好的节能效果。其比对效果见下表:

非晶纳米晶合金材料的工艺技术、产业化和应用

非晶纳米晶合金材料的工艺技术、产业化和应用 自从1960年Duwez教授等人发明液态金属快淬技术制取Au-Si非晶合金和1966年发明Fe-P-C 非晶软磁合金以来,美国、日本、德国、前苏联和中国等相继开展了非晶合金的研究工作,并在20世纪70~80年代形成非晶合金研究开发的第一次热潮。由于非晶合金制备工艺简单独特、材料性能优异等显著优点,应用范围不断扩大,四十多年来一直是冶金和材料领域的研究热点之一。尤其在1988年日本Yashizawa教授等人在非晶化的基础上发明了纳米晶合金,从而开创了软磁材料的新纪元,大大促进了非晶材料制备设备、工艺技术的发展和材料开发应用,推动了非晶纳米晶产业的发展[1~3, 8]。 目前,利用快淬金属工艺技术制备的非晶材料已被广泛地应用于工业领域,除我们熟悉的磁性材料外,还有非晶钎焊材料、非晶催化材料、磁敏及传感器材料等;应用的材料形态有带材、丝材、粉末及薄膜等。现代科学技术的发展,也大大促进了非晶纳米晶产业的发展,不仅提高了非晶合金制带设备和工艺技术水平,使其生产设备和技术更加自动化、现代化,保证了产品的质量,提高了产品的技术含量,从而满足现代电子技术发展的需要,而且也促进了新技术新材料研究、开发、应用[1~9]。 1 国外非晶纳米晶产业概况 美国曾是世界上最大的非晶材料制造商,Honeywell公司Metglas业务部(前身为Allied Signal公司),是非晶材料制造技术的平板流技术专利所有者,年生产能力3万吨以上,实际年产1~2万吨,带材生产实现自动控制和自动卷取。2003年被日本日立金属公司收购。Honeywell公司Metglas业务部拥要两个独资工厂:美国Conway非晶金属制带厂和印度Gurgaon电子铁芯元件厂,两个合资公司:日本非晶质金属公司(NAMCO)和上海汉威非晶金属公司(SHZAM)。在美国Conway非晶金属制带厂,有年产万吨级非晶带材生产线两条,主要生产Metglas2605SA-1,最大带材宽度为250mm,配有自动在线卷取设备及年产千吨级和百吨级非晶带材生产线各一条,主要生产电子材料、钎焊材料和新材料,最大带材宽度为220 mm 和100 mm,配有自动在线卷取设备[6, 7]。 日本主要有Hitachi(日立金属公司)和Toshiba(东芝公司)。Hitachi公司是利用快淬技术在非晶化基础上制备纳米晶软磁合金材料的发明者,2003年收购了Honeywell公司的非晶金属部分(Metglas业务部),今后将是世界上最大非晶纳米晶材料生产供应商,产品包括目前所有的市售商品,尤其以铁基纳米晶(Finemet)的系列化产品占据世界非晶纳米晶领域的重要地位,它拥有一条配有自动在线卷取设备的非晶带材生产线,年生产能力达百吨,最大宽度为150 mm。Toshiba公司主要生产Co基非晶产品,带材质量和性能居世界领先地位,尤其是磁放大器类产品,在市场上占有相当地位。带材生产实现自动化,最大宽度在100 mm 左右[7]。 德国的真空熔炼公司(VAC)通过购买非晶纳米晶软磁合金专利许可证的方式获得生产许可,主要生产用于电子产品的Co基非晶和Fe基纳米晶材料,并在专利基础上研制开发出不同用途的新型合金材料。也是非晶纳米晶材料重要制造商之一。带材实现自动化生产,非晶带材最大宽度为150mm[7]。 在俄罗斯(前苏联),主要开发一些Co基非晶合金产品,近几年同韩国的由由公司合作开发应用Co基产品,虽然生产规模不太大,但设备及自动化技术水平不低。 国外非晶合金的自动化生产线如图1所示[7]。

非晶超微晶(纳米晶)合金知识简介

非晶超微晶(纳米晶)合金知识简介 非晶超微晶(纳米晶)合金知识简介 铁基纳米晶合金是由铁元素为主,加入少量的Nb、Cu、Si、B元素所构成的合金经快速凝固工艺所形成的一种非晶态材料,这种非晶态材料经热处理后可获得直径为10-20纳米的微晶,弥散分布在非晶态的基体上,被称为超微晶或纳米晶材料. 纳米晶材料具有优异的综合磁性能:高饱和磁感(1.2T)、高初始磁导率(8万)、低Hc(0.32A/M), 高磁感下的高频损耗低(P0.5T/20kHz=30W/kg),电阻率为80 微欧厘米,比坡莫合金(50-60微欧厘米)高,经纵向或横向磁场处理,可得到高Br(0.9)或低Br值(1000Gs). 是目前市场上综合性能最好的材料;适用频率范围:50Hz-100kHz,最佳频率范围:20kHz-50kHz.广泛应用于大功率开关电源、逆变电源、磁放大器、高频变压器、高频变换器、高频扼流圈铁芯、互感器铁芯、漏电保护开关、共模电感铁芯.等. 非晶合金的特点及分类 非晶合金是一种导磁性能突出的材料,采用快速急冷凝固生产工艺,其物理状态表现为金属原子呈无序非晶体排列,它与硅钢的晶体结构完全不同,更利于被磁化和去磁。典型的非晶态合金含80%的铁,而其它成份是硼和硅。非晶合金材有下列特点:(1)非晶合金铁芯片厚度极薄,只有20至30um,填充系数较低,约为0.82。(2)非晶合金铁芯饱和磁密低。(3)非晶合金的硬度是硅钢片的5倍。(4)非晶合金铁芯材料对机械应力非常敏感,无论是张引力还是弯曲应力都会影响其磁性能。(5)非晶合金的磁致伸缩程度比硅钢片高约10%,而且不宜过度夹紧。非晶合金具有的高饱和磁感应强度、低损耗(相当于硅钢片的1/3~1/5)、低矫顽力、低激磁电流、良好的温度稳定性等特点。 非晶合金可以从化学成分上划分成以下几类: (1)铁基非晶合金(Fe-based amorphous alloys) 铁基非晶合金是由80%Fe及20%Si,B类金属元素所构成,它具有高饱和磁感应强度(1.54T),铁基非晶合金与硅钢的损耗比较:磁导率、激磁电流和铁损等各方面都优于硅钢片的特点,特别是铁损低(为取向硅钢片的1/3-1/5),代替硅钢做配电变压器可节能60-70%。铁基非晶合金的带材厚度为0.03mm左右,广泛应用于配电变压器、大功率开关电源、脉冲变压器、磁放大器、中频变压器及逆变器铁芯,适合于10kHz 以下频率使用。 (2)铁镍基、钴基非晶合金(Fe-Ni based-amorphous alloy) 铁镍基非晶合金是由40%Ni、40%Fe及20%类金属元素所构成,它具有中等饱和磁感应强度〔0.8T〕、较高的初始磁导率和很高的最大磁导率以及高的机械强度和优良的韧性。在中、低频率下具有低的铁损。空气中热处理不发生氧化,经磁场退火后可得到很好的矩形回线。价格比1J79便宜30-50%。铁镍基非晶合金的应用范围与中镍坡莫合金相对应,但低铁损和高的机械强度远比晶态合金优越;代替1J79,广泛用于漏电开关、精密电流互感器铁芯、磁屏蔽等。 (3) 铁基纳米晶合金(Nanocrystalline alloy) 铁基纳米晶合金是由铁元素为主,加入少量的Nb、Cu、Si、B元素所构成的合金经快速凝固工艺所形成的一种非晶态材料,纳米晶材料具有优异的综合磁性能:高饱和磁感(1.2T)、高初始磁导率(8×104)、低Hc(0.32A/M),高磁感下的高频损耗低(P0.5T/20kHz=30W/kg),电阻率为80μΩ/cm,比坡莫合金(50-60μΩ/cm)高,经纵向或横向磁场处理,可得到高Br(0.9)或低Br值(1000Gs)。是目前市场上综合性能最好的材料;适用频率范围:50Hz-100kHz,最佳频率范围:20kHz-50kHz 与传统材料的比较

非晶合金的特点、分类、应用、可行性分析

非晶纳米晶软磁合金及其应用 Amorphous and nanocrystalline soft magnetic alloys and its application 陈文智 1 非晶合金的特点 由于非晶合金的无序结构,使其具有一些独特的性质: 高强韧性:明显高于传统的钢铁材料,可以作复合增强材料,如钓鱼杆等。国外已经把块状非晶合金应用于高尔夫球击球拍头和微型齿轮。非晶合金丝材可用在结构零件中,起强化作用。 优良的磁性:与传统的金属磁性材料相比,由于非晶合金原子排列无序,没有晶体的各向异性,而且电阻率高,因此具有高的磁导率、低的损耗,是优良的软磁材料,代替硅钢、坡莫合金和铁氧体等作为变压器铁心、互感器、传感器等,可以大大提高变压器效率、缩小体积、减轻重量、降低能耗。非晶合金的磁性能实际上是迄今为止非晶合金最主要的应用领域,下面还将详细介绍。 简单的制造工艺:以传统的薄钢板为例,从炼钢、浇铸、钢锭开坯、初轧、退火、热轧、退火、酸洗、精轧、剪切到薄板成品,需要若干工艺环节、数十道工序。由于环节多,工艺繁杂,传统的钢铁企业都是耗能大户和污染大户,有"水老虎"和"电老虎"之称。而非晶合金的制造是在炼钢之后直接喷带,只需一步就制造出了薄带成品,工艺大大简化,节约了大量宝贵的能源,同时无污染物排放,对环境保护非常有利。正是由于非晶合金制造过程节能,同时它的磁性能优良,降低变压器使用过程中的损耗,因此被称为绿色材料和二十一世纪的材料。 2 非晶合金的分类 磁性非晶合金可以从化学成分上划分成以下几大类: 铁基非晶合金:主要元素是铁、硅、硼、碳、磷等。它们的特点是磁性强(饱和磁感应强度可达1.4T-1.7T)、软磁性能优于硅钢片,价格便宜,最适合替代硅钢片,作为中低频变压器和电感器铁心(一般在15千赫兹以下)。 铁镍基非晶合金:主要由铁、镍、硅、硼、磷等组成,它们的磁性比较弱(饱和磁感应强度大约为1T以下),价格较贵,但导磁率比较高,可以代替硅钢片

非晶纳米晶

机械合金化制备纳米晶与非晶 Al-Pb 系粉末 摘要:采用 X 射线衍射(XRD)、透射电镜(TEM)研究了球料比为 8:1、转速 280 r/min 和球料比为 25:1、转速 450r/min 条件下经不同球磨时间后混合粉末的相变、晶粒大小和微观形貌等。结果表明:通过机械合金化可以制备出Al-15%Pb-4%Si-1%Sn-1.5%Cu 纳米晶粉末,而且球磨导致了合金粉体非晶化,在球磨过程中混合粉体首先细化、合金化和纳米晶化,然后部分纳米晶转变为非晶;在机械合金化过程中球料比越大、转速越高,即给球磨系统供给的能量越大,则混合粉末获得纳米晶的时间越短;基于多层非晶化模型讨论了ΔH mix≈1.34 的情况下 Al-Pb 非晶形成的机制,指出在机械合金化过程中 Al-Pb 非晶形成并非需要ΔH mix<<0,其非晶化驱动力主要由浓度梯度提供。 1 前言 Al-Pb 系轴瓦合金比 Al-Sn 系轴瓦合金更容易在摩擦表面形成铅自润滑膜,表面性能更优越,且 Pb 的价格仅为 Sn 的 1/10~1/20;同时铝基轴瓦材料的疲劳强度约为巴氏合金的两倍,具有质轻、高导热性、高耐腐蚀性和良好的摩擦磨损性能等特点。因此 Al-Pb 系合金被认为是具有前途的轴瓦材料之一,研究开发新型的 Al-Pb 系耐磨合金具有重要的技术意义和经济意义。 但由于 Al 与 Pb 在室温不互溶,而且在高温也存在较宽的固溶间隙,同时 Al 与 Pb 之间较大的密度差异以及凝固点的差异,导致了用常规方法难以制备出Pb 粒子细小均匀弥散分布在 Al 基体上的 Al-Pb 轴瓦合金。而通过机械合金化可制备出 Pb 粒子细小均匀弥散分布的 Al-Pb 轴瓦合金[1]。 研究表明[2~4]:在 Al-Pb 二元合金中添加一定量的其它组元,可以进一步提高合金的性能,使其抗摩擦磨损性能优于纯二组元的 Al-Pb 合金。例如,在 Al-Pb二元合金中加入少量的Sn 可以提高 Pb 相的抗腐蚀性能;Cu 可以提高基体的强度;Si 可以提高 Al-Pb 合金 的磨损抗力和提高基体强度。因此,研究多组元 Al-Pb系合金对于研制高性能轴瓦材料具有重要意义。本实验将对 Al-Pb-Si-Sn-Cu 系混合粉末的机械合金化过程进行研究,并采用多层复合非晶模型对该系统形成非晶的机理进行研究。 2 实验方法 将纯度(质量分数)为 99.0%Al,99.9%Pb,99.9%Si,99.7%Cu,99.9%Sn,尺寸为 0.074 mm 的原始粉末按Al-15%Pb-4%Si-1%Sn-1.5%Cu( 质量分数,下同 ) 混合,并加入 1%的过程控制剂硬脂酸(PCA),在搅拌式高能球磨机中进行球磨,球罐为不锈钢。采用直径为 6 mm 的 GCr15 轴承钢球做研磨球,球磨的装填系数为 0.5,球磨过程始终在氩气保护和循环水冷却的条件下进行。球料比和球磨转速选用两种参数:球料比 25:1,球磨转速 450 r/min;球料比 8:1,球磨转速 280 r/min。 采用 Rigaku D/max-3C 型 X 射线衍射仪对混合粉末的组织结构和晶粒尺寸进行分析,采用CuKα辐射,并根据XRD 的半高宽计算出晶粒的大小。其计算公式为[5]: θ λ θsin ε Bcos+ .0 =d,其中 d 为晶粒尺寸,单位 nm;ε为晶格畸变量;λ为 4 94 / 衍射波长;其值λ=0.1540598 nm;B 为扣除非球磨因素(例如仪器、测量条件、原始粉末的畸变等)引起宽化后的值,用Warren 法计算:2S2M2B = B?B,其中 BS为原始粉末衍射峰半高宽值,BM为球磨粉末相应峰的半高宽值。采用 JEM-200CX 型透射电镜(TEM)分析了微观结构形貌,相机常数为 1.62 mm·nm。 3 分析与讨论 3.1 球磨粉末的 XRD 分析 图 1 是 Al-15Pb-4Si-1Sn-1.5Cu 混合粉末在不同球磨工艺和经不同球磨时间后的 X 射线

非晶纳米晶带材

“非晶纳米晶”是对“原子抗菌技术”的简称,是由日本东北大学和北京航空航天大学基于航天应用共同研发的最新科研成果,是一种最新的航天抗菌材料技术。非晶纳米晶带材哪家好?您可以选择安徽华晶机械有限公司,下面小编为您简单介绍,希望给您带来一定程度上的帮助。 “非晶纳米晶”是对一种新型材料原子排列结构状态的描述,该状态的金属及合金的原子处于高能量的极限状态,其原子能够逸出表面,产生具有杀菌活性的高能量原子及原子团(这些原子团大小仅为普通细菌和真菌的十几万分之一),可迅速进入病菌细胞内核,破坏细菌的DNA结构、阻止其遗传物质的复制的模式达到杀菌和抑菌效果。经中国科学院理化技术研究所抗菌材料检测中心的检测报告显示,该类材料杀菌有效率高达99.9%,特有的原理、功效及片状构造突破了传统的药物杀菌范畴。

非晶纳米晶材料主要在航空航天领域使用,主要用作宇航员宇航服材料技术,用于应对外太空可能出现的各种不利环境,保护宇航员不受外界病菌侵害。 纳米晶材料由纳米级尺寸(1~10nm)的晶体所组成的材料。由于晶体极细,故晶界可占整个材料的50%或更多。其原子排列既不同于有序的结晶态,也不同于无序的非晶态(玻璃态)。其性能也不同于相同成分的晶体或非晶体。 安徽华晶机械有限公司位于安庆长江大桥经济开发区。是人民解放军第4812工厂全资子公司。公司经营以机械制造为主,拥有各类专业生产、检验试验设备94台(套),涉及铸造、橡胶制品、压力容器、制造等多个行业,主要从事非晶软磁设备、空压机及气源设备、橡胶件(含特种橡胶件)、餐余垃圾处理设备、铸件、机械加工等产品的研制、生产、经营和服务。

自成立以来,公司上下高度重视技术创新和产品结构升级工作,建立了以市场为导向,努力满足用户需求的产品研发体系。公司坚持以跨越发展的思想为指导,秉承敬业、高效、求实、创新的优良传统,继续依托军工技术和“中”牌品质,为广大新老客户提供更优良的产品和服务。

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