AT89S52单片概述中英文资料对照外文翻译文献综述

AT89S52单片概述

中英文资料对照外文翻译文献综述

英文原文资料：

The Description of MCU

MCU Description

SCM is also known as micro-controller (Microcontroller Unit), commonly used letters of the acronym MCU MCU that it was first used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. INTEL's Z80 is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors have parted ways.

Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, because the cost is not satisfactory but have not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90's dedicated processor, while the average model prices fall to one U.S. dollars, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core

processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems.

SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 SCM, complex industrial control systems may even have hundreds of SCM in the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beings

Single chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a micro-computer, and computer than just the lack of a microcontroller I / O devices. General talk: a chip becomes a computer. Its small size, light weight, cheap, for the study, application and development of facilities provided. At the same time, learning to use the MCU is to understand the principle and structure of the computer the best choice.

SCM and the computer functions internally with similar modules, such as CPU, memory, parallel bus, the same effect as well, and hard disk memory devices, and different is its performance of these components were relatively weak many of our home computer, but the price is low , usually not more than 10 yuan you can do with it ...... some control for a class is not very complicated electrical work is enough of. We are using automatic drum washing machine, smoke hood, VCD and so on appliances which could see its shadow! ...... It is primarily as a control section of the core components

It is an online real-time control computer, control-line is that the scene is needed is a stronger anti-jamming ability, low cost, and this is, and off-line computer (such as home PC), the main difference.

Single chip

MCU is through running, and can be modified. Through different procedures to achieve different functions, in particular special unique features, this is another device much effort needs to be done, some great efforts are very difficult to do. A not very

complex functions if the 50's with the United States developed 74 series, or the 60's CD4000 series of these pure hardware buttoned, then the circuit must be a large PCB board! But if the United States if the 70's with a series of successful SCM market, the result will be a drastic change! Just because you are prepared by microcomputer programs can achieve high intelligence, high efficiency and high reliability!

As the microcontroller on the cost-sensitive, so now the dominant software or the lowest level assembly language, which is the lowest level in addition to more than binary machine code language, and as so low why is the use? Many high-level language has reached the level of visual programming Why is not it? The reason is simply that there is no home computer as a single chip CPU, not as hard as a mass storage device. A visualization of small high-level language program which even if only one button, will reach tens of K of size! For the home PC's hard drive in terms of nothing, but in terms of the MCU is not acceptable. SCM in the utilization of hardware resources to be very high for the job so although the original is still in the compilation of a lot of use. The same token, if the giant computer operating system and applications run up to get home PC, home PC, also can not afford to.

Can be said that the twentieth century across the three "power" era, that is, the age of electricity, the electronic age and has entered into the computer age. However, this computer, usually refers to the personal computer, referred to as PC. It consists of the host, keyboard, monitor and other components. Another type of computer, most people do not know how. This computer is to give all kinds of intelligent machines single chip (also known as micro-controller). As the name suggests, this computer system took only a minimal integrated circuit, can be a simple operation and control. Because it is small, usually hidden in the charged mechanical "stomach" in. It is in the device, like the human brain plays a role, it goes wrong, the whole plant was paralyzed. Now, this microcontroller has a very broad field of use, such as smart meters, real-time industrial control, communications equipment, navigation systems, and household appliances. Once all kinds of products were using SCM, can serve to upgrade the effectiveness of products, often in the product name preceded by the adjective - "intelligent," such as intelligent washing machines. Now some technical personnel of factories or other amateur electronics developers to engage in out of certain products, not the circuit is too complicated, that function is too simple and can easily be copied. The reason may be stuck in the product did not use a microcontroller or other programmable logic device.

SCM history

SCM was born in the late 20th century, 70, experienced SCM, MCU, SoC three stages.

First model

1.SCM the single chip microcomputer (Single Chip Microcomputer) stage, mainly seeking the best of the best single form of embedded systems architecture. "Innovation model" success, laying the SCM and general computer completely different path of development. In the open road of independent development of embedded systems, Intel Corporation contributed.

2.MCU the micro-controller (Micro Controller Unit) stage, the main direction of technology development: expanding to meet the embedded applications, the target system requirements for the various peripheral circuits and interface circuits, highlight the object of intelligent control. It involves the areas associated with the object system, therefore, the development of MCU's responsibility inevitably falls on electrical, electronics manufacturers. From this point of view, Intel faded MCU development has its objective factors. In the development of MCU, the most famous manufacturers as the number of Philips Corporation.

Philips company in embedded applications, its great advantage, the MCS-51 single-chip micro-computer from the rapid development of the micro-controller. Therefore, when we look back at the path of development of embedded systems, do not forget Intel and Philips in History.

Embedded Systems

Embedded system microcontroller is an independent development path, the MCU important factor in the development stage, is seeking applications to maximize the solution on the chip; Therefore, the development of dedicated single chip SoC trend of the natural form. As the microelectronics, IC design, EDA tools development, application system based on MCU SoC design have greater development. Therefore, the understanding of the microcontroller chip microcomputer can be, extended to the single-chip micro-controller applications.

MCU applications

SCM now permeate all areas of our lives, which is almost difficult to find traces of the field without SCM. Missile navigation equipment, aircraft, all types of instrument control, computer network communications and data transmission, industrial automation, real-time process control and data processing, extensive use of various

smart IC card, civilian luxury car security system, video recorder, camera, fully automatic washing machine control, and program-controlled toys, electronic pet, etc., which are inseparable from the microcontroller. Not to mention the area of robot control, intelligent instruments, medical equipment was. Therefore, the MCU learning, development and application of the large number of computer applications and intelligent control of the scientists, engineers.

The single-chip microcomputer AT89S52 MCU as an example, the pair for further description:

AT89S52 MCU

Features

? Compatible with MCS-51 Products

? 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 10,000 Write/Erase Cycles

? 4.0V to 5.5V Operating Range

? Fully Static Operation: 0 Hz to 33 MHz

? Three-level Program Memory Lock

? 256 x 8-bit Internal RAM

? 32 Programmable I/O Lines

? Three 16-bit Timer/Counters

? Eight Interrupt Sources

? Full Duplex UART Serial Channel

? Low-power Idle and Power-down Modes

? Interrupt Recovery from Pow er-down Mode

? Watchdog Timer ? Dual Data Pointer

? Power-off Flag ? Fast Programming Time

? Flexible ISP Programming (Byte and Page Mode)

? Green (Pb/Halide-free) Packaging Option

1.Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the

program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

2.Pin Description

VCC ：Supply voltage.

GND ：Ground.

Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.

Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.

Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table.

Table2

RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to exter-nal data memory.

EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2：Output from the inverting oscillator amplifier.

3.Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

3.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

3.2 Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

4.Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To

enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.

4.1 Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

4.2 WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the

WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

5. UART

The UART in the AT89S52 operates the same way as the UART in the AT89C51 and AT89C52. For further information on the UART operation, please click on the document link below:

https://www.sodocs.net/doc/9515501510.html,/dyn/resources/prod_documents/DOC4316.PDF

6. Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:

https://www.sodocs.net/doc/9515501510.html,/dyn/resources/prod_documents/DOC4316.PDF

7. Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

7.1 Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi-tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.

7.2 Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD . Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin. Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 10-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in

RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

8. Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol -lowing equation.

The Timer can be configured for either timer or counter operation. In most applications, it is con-figured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.

This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter-rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = 16

Modes 1 and 3Oscillator Frequency Baud Rate 32[65536-RCAP2H,RCAP2L]

=?

written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.

9. Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency). To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen-erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.

10. Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the Oscilator Frequency Clock-Out Frequency=4[65536-(RCAP2H,RCAP2L)]

timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

11. Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

12. Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

13. Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

土木工程类专业英文文献及翻译

PA VEMENT PROBLEMS CAUSED BY COLLAPSIBLE SUBGRADES By Sandra L. Houston,1 Associate Member, ASCE (Reviewed by the Highway Division) ABSTRACT: Problem subgrade materials consisting of collapsible soils are com- mon in arid environments, which have climatic conditions and depositional and weathering processes favorable to their formation. Included herein is a discussion of predictive techniques that use commonly available laboratory equipment and testing methods for obtaining reliable estimates of the volume change for these problem soils. A method for predicting relevant stresses and corresponding collapse strains for typical pavement subgrades is presented. Relatively simple methods of evaluating potential volume change, based on results of familiar laboratory tests, are used. INTRODUCTION When a soil is given free access to water, it may decrease in volume, increase in volume, or do nothing. A soil that increases in volume is called a swelling or expansive soil, and a soil that decreases in volume is called a collapsible soil. The amount of volume change that occurs depends on the soil type and structure, the initial soil density, the imposed stress state, and the degree and extent of wetting. Subgrade materials comprised of soils that change volume upon wetting have caused distress to highways since the be- ginning of the professional practice and have cost many millions of dollars in roadway repairs. The prediction of the volume changes that may occur in the field is the first step in making an economic decision for dealing with these problem subgrade materials. Each project will have different design considerations, economic con- straints, and risk factors that will have to be taken into account. However, with a reliable method for making volume change predictions, the best design relative to the subgrade soils becomes a matter of economic comparison, and a much more rational design approach may be made. For example, typical techniques for dealing with expansive clays include: (1) In situ treatments with substances such as lime, cement, or fly-ash; (2) seepage barriers and/ or drainage systems; or (3) a computing of the serviceability loss and a mod- ification of the design to "accept" the anticipated expansion. In order to make the most economical decision, the amount of volume change (especially non- uniform volume change) must be accurately estimated, and the degree of road roughness evaluated from these data. Similarly, alternative design techniques are available for any roadway problem. The emphasis here will be placed on presenting economical and simple methods for: (1) Determining whether the subgrade materials are collapsible; and (2) estimating the amount of volume change that is likely to occur in the 'Asst. Prof., Ctr. for Advanced Res. in Transp., Arizona State Univ., Tempe, AZ 85287. Note. Discussion open until April 1, 1989. To extend the closing date one month,

英文文献翻译

中等分辨率制备分离的 快速色谱技术 W. Clark Still,* Michael K a h n , and Abhijit Mitra Departm(7nt o/ Chemistry, Columbia Uniuersity,1Veu York, Neu; York 10027 ReceiLied January 26, 1978 我们希望找到一种简单的吸附色谱技术用于有机化合物的常规净化。这种技术是适于传统的有机物大规模制备分离，该技术需使用长柱色谱法。尽管这种技术得到的效果非常好，但是其需要消耗大量的时间，并且由于频带拖尾经常出现低复原率。当分离的样本剂量大于1或者2g时，这些问题显得更加突出。近年来，几种制备系统已经进行了改进，能将分离时间减少到1-3h，并允许各成分的分辨率ΔR f≥（使用薄层色谱分析进行分析）。在这些方法中，在我们的实验室中，媒介压力色谱法1和短柱色谱法2是最成功的。最近，我们发现一种可以将分离速度大幅度提升的技术，可用于反应产物的常规提纯，我们将这种技术称为急骤色谱法。虽然这种技术的分辨率只是中等（ΔR f≥），而且构建这个系统花费非常低，并且能在10-15min内分离重量在的样本。4 急骤色谱法是以空气压力驱动的混合介质压力以及短柱色谱法为基础，专门针对快速分离，介质压力以及短柱色谱已经进行了优化。优化实验是在一组标准条件5下进行的，优化实验使用苯甲醇作为样本，放在一个20mm*5in.的硅胶柱60内，使用Tracor 970紫外检测器监测圆柱的输出。分辨率通过持续时间（r）和峰宽（w,w/2）的比率进行测定的（Figure 1），结果如图2-4所示，图2-4分别放映分辨率随着硅胶颗粒大小、洗脱液流速和样本大小的变化。

土木工程外文翻译

转型衰退时期的土木工程研究 Sergios Lambropoulosa[1], John-Paris Pantouvakisb, Marina Marinellic 摘要 最近的全球经济和金融危机导致许多国家的经济陷入衰退，特别是在欧盟的周边。这些国家目前面临的民用建筑基础设施的公共投资和私人投资显著收缩，导致在民事特别是在民用建筑方向的失业。因此，在所有国家在经济衰退的专业发展对于土木工程应届毕业生来说是努力和资历的不相称的研究，因为他们很少有机会在实践中积累经验和知识，这些逐渐成为过时的经验和知识。在这种情况下，对于技术性大学在国家经济衰退的计划和实施的土木工程研究大纲的一个实质性的改革势在必行。目的是使毕业生拓宽他们的专业活动的范围，提高他们的就业能力。 在本文中，提出了土木工程研究课程的不断扩大，特别是在发展的光毕业生的潜在的项目，计划和投资组合管理。在这个方向上，一个全面的文献回顾，包括ASCE体为第二十一世纪，IPMA的能力的基础知识，建议在其他：显著增加所提供的模块和项目管理在战略管理中添加新的模块，领导行为，配送管理，组织和环境等；提供足够的专业训练五年的大学的研究；并由专业机构促进应届大学生认证。建议通过改革教学大纲为土木工程研究目前由国家技术提供了例证雅典大学。 1引言 土木工程研究（CES）蓬勃发展，是在第二次世界大战后。土木工程师的出现最初是由重建被摧毁的巨大需求所致，目的是更多和更好的社会追求。但是很快，这种演变一个长期的趋势，因为政府为了努力实现经济发展，采取了全世界的凯恩斯主义的理论，即公共基础设施投资作为动力。首先积极的结果导致公民为了更好的生活条件（住房，旅游等）和增加私人投资基础设施而创造机会。这些现象再国家的发展中尤为为明显。虽然前景并不明朗（例如，世界石油危机在70年代），在80年代领先的国家采用新自由主义经济的方法（如里根经济政策），这是最近的金融危机及金融危机造成的后果（即收缩的基础设施投资，在技术部门的高失业率），消除发展前途无限的误区。 技术教育的大学所认可的大量研究土木工程部。旧学校拓展专业并且新的学校建成，并招收许多学生。由于高的职业声望，薪酬，吸引高质量的学校的学生。在工程量的增加和科学技术的发展，导致到极强的专业性，无论是在研究还是工作当中。结构工程师，液压工程师，交通工程师等，都属于土木工程。试图在不同的国家采用专业性的权利，不同的解决方案，，从一个统一的大学学历和广泛的专业化的一般职业许可证。这个问题在许多其他行业成为关键。国际专业协会的专家和机构所确定的国家性检查机构，经过考试后，他们证明不仅是行业的新来者，而且专家通过时间来确定进展情况。尽管在很多情况下，这些证书虽然没有国家接受，他们赞赏和公认的世界。 在试图改革大学研究（不仅在土木工程）更接近市场需求的过程中，欧盟确定了1999博洛尼亚宣言，它引入了一个二能级系统。第一级度（例如，一个三年的学士）是进入

文献综述,外文翻译,论文网站

文献综述怎么写 1) 什么是文献综述? 文献综述是研究者在其提前阅读过某一主题的文献后，经过理解、整理、融会贯通，综合分析和评价而组成的一种不同于研究论文的文体。 2) 文献综述的写作要求 1、文献综述的格式 文献综述的格式与一般研究性论文的格式有所不同。这是因为研究性的论文注重研究的方法和结果，而文献综述介绍与主题有关的详细资料、动态、进展、展望以及对以上方面的评述。因此文献综述的格式相对多样，但总的来说，一般都包含以下四部分：即前言、主题、总结和参考文献。撰写文献综述时可按这四部分拟写提纲，再根据提纲进行撰写工作。 前言，要用简明扼要的文字说明写作的目的、必要性、有关概念的定义，综述的范围，阐述有关问题的现状和动态，以及目前对主要问题争论的焦点等。前言一般200-300字为宜，不宜超过500字。 正文，是综述的重点，写法上没有固定的格式，只要能较好地表达综合的内容，作者可创造性采用诸多形式。正文主要包括论据和论证两个部分，通过提出问题、分析问题和解决问题，比较不同学者对同一问题的看法及其理论依据，进一步阐明问题的来龙去脉和作者自己的见解。当然，作者也可从问题发生的历史背景、目前现状、发展方向等提出文献的不同观点。正文部分可根据内容的多少可分为若干个小标题分别论述。 小结，是结综述正文部分作扼要的总结，作者应对各种观点进行综合评价，提出自己的看法，指出存在的问题及今后发展的方向和展望。内容单纯的综述也可不写小结。 参考文献，是综述的重要组成部分。一般参考文献的多少可体现作者阅读文献的广度和深度。对综述类论文参考文献的数量不同杂志有不同的要求，一般以30条以内为宜，以最近3-5年内的最新文献为主。 2、文献综述规定 1. 为了使选题报告有较充分的依据，要求硕士研究生在论文开题之前作文献综述。 2. 在文献综述时，研究生应系统地查阅与自己的研究方向有关的国内外文献。通常阅读文献不少于30篇，且文献搜集要客观全面 3. 在文献综述中，研究生应说明自己研究方向的发展历史，前人的主要研究成果，存在的问题及发展趋势等。 4. 文献综述要条理清晰，文字通顺简练。 5. 资料运用恰当、合理。文献引用用方括号[ ]括起来置于引用词的右上角。 6. 文献综述中要有自己的观点和见解。不能混淆作者与文献的观点。鼓励研究生多发现问题、多提出问题、并指出分析、解决问题的可能途径，针对性强。 7. 文献综述不少于3000字。 3、注意事项 ⒈搜集文献应尽量全。掌握全面、大量的文献资料是写好综述的前提，否则，随便搜集一点资料就动手撰写是不可能写出好的综述。 ⒉注意引用文献的代表性、可靠性和科学性。在搜集到的文献中可能出现观点雷同，有的文献在可靠性及科学性方面存在着差异，因此在引用文献时应注意选用代表性、可靠性和科学性较好的文献。 ⒊引用文献要忠实文献内容。由于文献综述有作者自己的评论分析，因此在撰写时应分清作者的观点和文献的内容，不能篡改文献的内容。引用文献不过多。文献综述的作者引用间接文献的现象时有所见。如果综述作者从他人引用的参考文献转引过来，这些文献在他人

酒店服务质量管理外文文献翻译

文献出处：Borkar S, Koranne S. Study of Service Quality Management in Hotel Industry [J]. Pacific Business Review International, 2014, 6(9): 21-25. 原文 Study of Service Quality Management in Hotel Industry Borkar; Sameer Abstract It is an attempt to understand the role of quality improvement process in hospitality industry and effectiveness in making it sustainable business enterprise. It is a survey of the presently adopted quality management tools which are making the hotels operations better focused and reliable and meet the customer expectations. Descriptive research design is used to know the parameters of service quality management in hospitality industry. Exploratory research design is undertaken to dig out the service quality management practices and its effectiveness. Data analysis is done and presented; hypothesis is tested against the collected data. Since the industry continuously tries to improve upon their services to meet the levels of customer satisfaction; Study presents tools for continuous improvement process and how it benefits all the stake holders. It can be inferred from the study that the hotel implement continuous improvement process and quality management tools to remain competitive in the market. The study involves hotels of highly competitive market with limited number of respondents. This limits the study to hotel industry and has scope of including other hospitality service providers as well. Keywords:Customer Satisfaction, Perception, Performance Measurement, Continuous, Improvement Process. Introduction It has brought paradigm shifts in the operations of hospitality industry. The overall perspective of the industry is changed due to introduction of new techniques

土木工程岩土类毕业设计外文翻译

姓名： 学号： 10447425 X X 大学 毕业设计（论文）外文翻译 （2014届） 外文题目Developments in excavation bracing systems 译文题目开挖工程支撑体系的发展 外文出处Tunnelling and Underground Space Technology 31 (2012) 107–116 学生XXX 学院XXXX 专业班级XXXXX 校内指导教师XXX 专业技术职务XXXXX 校外指导老师专业技术职务 二○一三年十二月

开挖工程支撑体系的发展 1.引言 几乎所有土木工程建设项目（如建筑物，道路，隧道，桥梁，污水处理厂，管道，下水道）都涉及泥土挖掘的一些工程量。往往由于由相邻的结构，特性线，或使用权空间的限制，必须要一个土地固定系统，以允许土壤被挖掘到所需的深度。历史上，许多挖掘支撑系统已经开发出来。其中，现在比较常见的几种方法是：板桩，钻孔桩墙，泥浆墙。 土地固定系统的选择是由技术性能要求和施工可行性（例如手段，方法）决定的，包括执行的可靠性，而成本考虑了这些之后，其他问题也得到解决。通常环境后果（用于处理废泥浆和钻井液如监管要求）也非常被关注（邱阳、1998）。 土地固定系统通常是建设项目的较大的一个组成部分。如果不能按时完成项目，将极大地影响总成本。通常首先建造支撑，在许多情况下，临时支撑系统是用于支持在挖掘以允许进行不断施工，直到永久系统被构造。临时系统可以被去除或留在原处。 打桩时，因撞击或振动它们可能会被赶入到位。在一般情况下，振动是最昂贵的方法，但只适合于松散颗粒材料，土壤中具有较高电阻（例如，通过鹅卵石）的不能使用。采用打入桩系统通常是中间的成本和适合于软沉积物（包括粘性和非粘性），只要该矿床是免费的鹅卵石或更大的岩石。 通常，垂直元素（例如桩）的前安装挖掘工程和水平元件（如内部支撑或绑回）被安装为挖掘工程的进行下去，从而限制了跨距长度，以便减少在垂直开发弯矩元素。在填充情况下，桩可先设置，从在斜坡的底部其嵌入悬挑起来，安装作为填充进步水平元素（如搭背或土钉）。如果滞后是用来保持垂直元素之间的土壤中，它被安装为挖掘工程的进行下去，或之前以填补位置。 吉尔- 马丁等人（2010）提供了一个数值计算程序，以获取圆形桩承受轴向载荷和统一标志（如悬臂桩）的单轴弯矩的最佳纵筋。他们开发的两种优化流程：用一个或两个直径为纵向钢筋。优化增强模式允许大量减少的设计要求钢筋的用量，这些减少纵向钢筋可达到50％相对传统的，均匀分布的加固方案。 加固桩集中纵向钢筋最佳的位置在受拉区。除了节约钢筋，所述非对称加强钢筋图案提高抗弯刚度，通过增加转动惯量的转化部分的时刻。这种增加的刚性可能会在一段时间内增加的变形与蠕变相关的费用。评估相对于传统的非对称加强桩的优点，对称，钢筋桩被服务的条件下全面测试来完成的，这种试验是为了验证结构的可行性和取得的变形的原位测量。 基于现场试验中，用于优化的加强图案的优点浇铸钻出孔（CIDH）在巴塞罗那的

计算机网络-外文文献-外文翻译-英文文献-新技术的计算机网络

New technique of the computer network Abstract The 21 century is an ages of the information economy, being the computer network technique of representative techniques this ages, will be at very fast speed develop soon in continuously creatively, and will go deep into the people's work, life and study. Therefore, control this technique and then seem to be more to deliver the importance. Now I mainly introduce the new technique of a few networks in actuality live of application. keywords Internet Network System Digital Certificates Grid Storage 1. Foreword Internet turns 36, still a work in progress Thirty-six years after computer scientists at UCLA linked two bulky computers using a 15-foot gray cable, testing a new way for exchanging data over networks, what would ultimately become the Internet remains a work in progress. University researchers are experimenting with ways to increase its capacity and speed. Programmers are trying to imbue Web pages with intelligence. And work is underway to re-engineer the network to reduce Spam (junk mail) and security troubles. All the while threats loom: Critics warn that commercial, legal and political pressures could hinder the types of innovations that made the Internet what it is today. Stephen Crocker and Vinton Cerf were among the graduate students who joined UCLA professor Len Klein rock in an engineering lab on Sept. 2, 1969, as bits of meaningless test data flowed silently between the two computers. By January, three other "nodes" joined the fledgling network.

土木工程外文翻译.doc

项目成本控制 一、引言 项目是企业形象的窗口和效益的源泉。随着市场竞争日趋激烈，工程质量、文明施工要求不断提高，材料价格波动起伏，以及其他种种不确定因素的影响，使得项目运作处于较为严峻的环境之中。由此可见项目的成本控制是贯穿在工程建设自招投标阶段直到竣工验收的全过程，它是企业全面成本管理的重要环节，必须在组织和控制措施上给于高度的重视，以期达到提高企业经济效益的目的。 二、概述 工程施工项目成本控制，指在项目成本在成本发生和形成过程中，对生产经营所消耗的人力资源、物资资源和费用开支，进行指导、监督、调节和限制，及时预防、发现和纠正偏差从而把各项费用控制在计划成本的预定目标之内，以达到保证企业生产经营效益的目的。 三、施工企业成本控制原则 施工企业的成本控制是以施工项目成本控制为中心，施工项目成本控制原则是企业成本管理的基础和核心，施工企业项目经理部在对项目施工过程进行成本控制时，必须遵循以下基本原则。 3.1 成本最低化原则。施工项目成本控制的根本目的，在于通过成本管理的各种手段，促进不断降低施工项目成本，以达到可能实现最低的目标成本的要求。在实行成本最低化原则时，应注意降低成本的可能性和合理的成本最低化。一方面挖掘各种降低成本的能力，使可能性变为现实；另一方面要从实际出发，制定通过主观努力可能达到合理的最低成本水平。 3.2 全面成本控制原则。全面成本管理是全企业、全员和全过程的管理，亦称“三全”管理。项目成本的全员控制有一个系统的实质性内容，包括各部门、各单位的责任网络和班组经济核算等等，应防止成本控制人人有责，人人不管。项目成本的全过程控制要求成本控制工作要随着项目施工进展的各个阶段连续 进行，既不能疏漏，又不能时紧时松，应使施工项目成本自始至终置于有效的控制之下。 3.3 动态控制原则。施工项目是一次性的，成本控制应强调项目的中间控制，即动态控制。因为施工准备阶段的成本控制只是根据施工组织设计的具体内容确

供应商质量管理文献翻译(外文翻译-中英对照)

互利共赢的供应商质量控制 前言 近年来，随着对供应链的重视，供应商管理正逐渐成为企业和学术界的关注对象，IS0９000族标准以及QS 9０00标准都对供应商的管理提出了相应的要求，与供应商管理有关的研究成果正逐渐增多，一些软件巨头也推出了供应商关系管理的软件，但是在这些研究成果和应用软件中，涉及到的供应商质量控制的内容只是一些最基本的要求，而供应商质量控制恰恰是供应商管理的最基本、最重要的内容。另一方而，质量管理界对质量控制的研究取得了大量的成果，遗憾的是这些成果大多依然局限于企业的内部控制，仅仅研究从企业内部各环节如何改善产品的质量，而基于供应链的角度来研究质量控制的成果尚不多见。因此，系统地研究经济全球化形势下供应商质量控制的理论与方法，将有助于推动我国企业产品质量的快速提高和供应链竞争优势的形成与巩固。 1、质量与企业共存 质量一直是一个随着时代的变化而不断变化的概念,人们对质量的认识也往往因关注点不同而有所不同。如，早在1908年，通用汽车公司的工程师们在皇家汽车俱乐部会员们的面前拆解了3辆凯迪拉克轿车，并把这些零件混在一起,而后从中选择零件重新组装成车，然后驾车绝尘而去。这令在场的会员极为震惊，认为凯迪拉克车质量之高令人惊叹。显然在当时，汽车零件具有互换性是一种了不起的质量特性,这也是福特公司的Ｎ型车和T型车取得辉煌成功的重要原因.时至今日，即使农用三轮车的零部件也具有极高的互换性，零部件的标准化和互换性已经是理所当然的事情，不再是吸引顾客的重要质量特性.可见质量的内涵是不断变化的.那么究竟什么是质量呢？ （１)市场竟争就是企业间对“顾客”的争夺，在日益激烈的“顾客"争夺战中，质量、价格、交付（交付日期、方式和手段）和服务是企业常用的四个法宝，其中质量是根本，离开质量其他三项将变得毫无意义，因此可以说质量己成为市场竞争的焦点.它反映了产品是否能够反映顾客需求、能否满足顾客需求，从面决定了产品的市场前途。有鉴于此，质量己成为一项全球性运动,世界上所有优秀企业无一不把质量作为企业战略的关键内容，从战略的角度来规划质量。 （2）对于企业经营者来说,认识到质量对企业的重要意义只是经营企业的第一步,重要的是如何利用科学的方法来保证产品和服务的质量，使顾客满意，来保证过程和工作的质量来获互利共炭的供应商质量控制得良好的业绩。 众所周知,企业管理是社会生产力发展到一定程度的历史产物,质量管理作为企业管理的组成部分,同样也是社会发展的客观要求，特别是顾客处于主导地位的今天,要使顾客满意，就必须有过硬的产品质量和服务质量，这就要求企业积极推行先进的质量管理理论与方法，不断进行质量管理创新. ２、企业与供应商质量控制 随着生产社会化的不断发展，企业的生产活动分工越来越细,专业化程度越来越强，促使生产技术水平越来越高,产品质量得到大幅度改善。通常，某一产品不可能由一个企业从最初的原材料开始加工直至形成顾客最终使用的产品，往往是通过多个企业分工协作来完成.另外，先进生产方式的广泛应用,如准时生产、敏捷制造、零库存等，使企业与供应商的关系愈加紧密，企业与供应商的关系也由单纯的买卖关系向互利共底的合作关系演变。 ISO 900０族标准自1987年诞生以来受到了世界各国的一致追捧,全球约５0多万家企业通过ISO90０1质量管理体系认证足以说明这套管理标准在引领国际管理潮流方面的巨大成功。在备受企业欢迎的新版标准ＩSO9000：2０00中，互利的供应商关系被作为八项质量管理原则之一，充分体现了供应商关系管理在企业经营实践中的作用和价值。企业要贯彻这一原则,就必须

土木工程专业外文文献及翻译

（ 二 〇 一 二 年 六 月 外文文献及翻译 题 目： About Buiding on the Structure Design 学生姓名： 学 院：土木工程学院 系 别：建筑工程系 专 业：土木工程(建筑工程方向) 班 级：土木08-4班 指导教师：

英文原文： Building construction concrete crack of prevention and processing Abstract The crack problem of concrete is a widespread existence but again difficult in solve of engineering actual problem, this text carried on a study analysis to a little bit familiar crack problem in the concrete engineering, and aim at concrete the circumstance put forward some prevention, processing measure. Keyword:Concrete crack prevention processing Foreword Concrete's ising 1 kind is anticipate by the freestone bone, cement, water and other mixture but formation of the in addition material of quality brittleness not and all material.Because the concrete construction transform with oneself, control etc. a series problem, harden model of in the concrete existence numerous tiny hole, spirit cave and tiny crack, is exactly because these beginning start blemish of existence just make the concrete present one some not and all the characteristic of quality.The tiny crack is a kind of harmless crack and accept concrete heavy, defend Shen and a little bit other use function not a creation to endanger.But after the concrete be subjected to lotus carry, difference in temperature etc. function, tiny crack would continuously of expand with connect, end formation we can see without the

变电站_外文翻译_外文文献_英文文献_变电站的综合概述

英文翻译 A comprehensive overview of substations Along with the economic development and the modern industry developments of quick rising, the design of the power supply system become more and more completely and system. Because the quickly increase electricity of factories, it also increases seriously to the dependable index of the economic condition, power supply in quantity. Therefore they need the higher and more perfect request to the power supply. Whether Design reasonable, not only affect directly the base investment and circulate the expenses with have the metal depletion in colour metal, but also will reflect the dependable in power supply and the safe in many facts. In a word, it is close with the economic performance and the safety of the people. The substation is an importance part of the electric power system, it is consisted of the electric appliances equipments and the Transmission and the Distribution. It obtains the electric power from the electric power system, through its function of transformation and assign, transport and safety. Then transport the power to every place with safe, dependable, and economical. As an important part of power’s transport and control, the transformer substation must change the mode of the traditional design and control, then can adapt to the modern electric power system, the development of modern industry and the of trend of the society life. Electric power industry is one of the foundations of national industry and national economic development to industry, it is a coal, oil, natural gas, hydropower, nuclear power, wind power and other energy conversion into electrical energy of the secondary energy industry, it for the other departments of the national economy fast and stable development of the provision of adequate power, and its level of development is a reflection of the country's economic development an important indicator of the level. As the power in the industry and the importance of the national economy, electricity transmission and distribution of electric energy used in these areas is an indispensable component.。Therefore, power transmission and distribution is critical. Substation is to enable superior power plant power plants or power after adjustments to the lower load of books is an important part of power transmission. Operation of its functions, the capacity of a direct impact on the size of the lower load power, thereby affecting the industrial production and power consumption.Substation system if a link failure, the system will protect the part of action. May result in power outages and so on, to the production and living a great disadvantage. Therefore, the substation in the electric power system for the protection of electricity reliability,

土木工程外文文献翻译

专业资料 学院： 专业：土木工程 姓名： 学号： 外文出处：Structural Systems to resist (用外文写) Lateral loads 附件：1.外文资料翻译译文；2.外文原文。

附件1：外文资料翻译译文 抗侧向荷载的结构体系 常用的结构体系 若已测出荷载量达数千万磅重，那么在高层建筑设计中就没有多少可以进行极其复杂的构思余地了。确实，较好的高层建筑普遍具有构思简单、表现明晰的特点。 这并不是说没有进行宏观构思的余地。实际上，正是因为有了这种宏观的构思，新奇的高层建筑体系才得以发展，可能更重要的是：几年以前才出现的一些新概念在今天的技术中已经变得平常了。 如果忽略一些与建筑材料密切相关的概念不谈，高层建筑里最为常用的结构体系便可分为如下几类： 1.抗弯矩框架。 2.支撑框架，包括偏心支撑框架。 3.剪力墙，包括钢板剪力墙。 4.筒中框架。 5.筒中筒结构。 6.核心交互结构。 7. 框格体系或束筒体系。 特别是由于最近趋向于更复杂的建筑形式，同时也需要增加刚度以抵抗几力和地震力，大多数高层建筑都具有由框架、支撑构架、剪力墙和相关体系相结合而构成的体系。而且，就较高的建筑物而言，大多数都是由交互式构件组成三维陈列。 将这些构件结合起来的方法正是高层建筑设计方法的本质。其结合方式需要在考虑环境、功能和费用后再发展，以便提供促使建筑发展达到新高度的有效结构。这并

不是说富于想象力的结构设计就能够创造出伟大建筑。正相反，有许多例优美的建筑仅得到结构工程师适当的支持就被创造出来了，然而，如果没有天赋甚厚的建筑师的创造力的指导，那么，得以发展的就只能是好的结构，并非是伟大的建筑。无论如何，要想创造出高层建筑真正非凡的设计，两者都需要最好的。 虽然在文献中通常可以见到有关这七种体系的全面性讨论，但是在这里还值得进一步讨论。设计方法的本质贯穿于整个讨论。设计方法的本质贯穿于整个讨论中。 抗弯矩框架 抗弯矩框架也许是低，中高度的建筑中常用的体系，它具有线性水平构件和垂直构件在接头处基本刚接之特点。这种框架用作独立的体系，或者和其他体系结合起来使用，以便提供所需要水平荷载抵抗力。对于较高的高层建筑，可能会发现该本系不宜作为独立体系，这是因为在侧向力的作用下难以调动足够的刚度。 我们可以利用STRESS，STRUDL 或者其他大量合适的计算机程序进行结构分析。所谓的门架法分析或悬臂法分析在当今的技术中无一席之地，由于柱梁节点固有柔性，并且由于初步设计应该力求突出体系的弱点，所以在初析中使用框架的中心距尺寸设计是司空惯的。当然，在设计的后期阶段，实际地评价结点的变形很有必要。 支撑框架 支撑框架实际上刚度比抗弯矩框架强，在高层建筑中也得到更广泛的应用。这种体系以其结点处铰接或则接的线性水平构件、垂直构件和斜撑构件而具特色，它通常与其他体系共同用于较高的建筑，并且作为一种独立的体系用在低、中高度的建筑中。