1.存储器访问指令
LDR
STR
LDR
Load 32-bit word to Memory.
Syntax LDR{cond} Rd, [Rn]
LDR{cond} Rd, [Rn, offset]
LDR{cond} Rd, [Rn, offset]!
LDR{cond} Rd, label
LDR{cond} Rd, [Rn], offset
Description LDR{cond} Rd, [Rn] (zero offset)
Rn is used as address value.
LDR{cond} Rd, [Rn, offset] (Pre-indexed offset)
Rn and offset are added and used as address value.
LDR{cond} Rd, [Rn, offset]{!} (Pre-indexed offset with update)
Rn and offset are added and used as address value. The new address value is written to Rn.
LDR{cond} Rd, label (Program-relative)
The assembler calculates the PC offset and generates LDR{cond} Rd, [R15, offset].
LDR{cond} Rd, [Rn], offset (Post-indexed offset)
Rn is used as address value. After memory transfer, the offset is added to Rn. Example
LDR R8,[R10] //loads r8 from the address in r10.
LDRNE R2,[R5,#960]! //(conditionally) loads r2 from a word 960 bytes above the address in r5, and increments r5 by 960.
LDR R0,localdata //loads a word located at label localdata STR
Store register 32-bit words to Memory. The address must be 32-bit word-aligned.
Syntax STR{cond} Rd, [Rn]
STR{cond} Rd, [Rn, offset]
STR{cond} Rd, [Rn, offset]!
STR{cond} Rd, label
STR{cond} Rd, [Rn], offset
Description STR{cond} Rd, [Rn] (zero offset)
Rn is used as address value.
STR{cond} Rd, [Rn, offset] (Pre-indexed offset)
Rn and offset are added and used as address value.
STR{cond} Rd, [Rn, offset]! (Pre-indexed offset with update)
Rn and offset are added and used as address value. The new address value is written to Rn.
STR{cond} Rd, label (Program-relative)
The assembler calculates the PC offset and generates STR{cond} Rd, [R15], offset.
STR{cond} Rd, [Rn], offset (Post-indexed offset)
Rn is used as address value. After memory transfer, the offset is added to Rn. Example LDR r8,[r10] //loads r8 from the address in r10.
LDRNE r2,[r5,#960]! //(conditionally) loads r2 from a word
//960 bytes above the address in r5, and
//increments r5 by 960.
STR r2,[r9,#consta-struc] //consta-struc is an expression evaluating
//to a constant in the range 0-4095.
STRB r0,[r3,-r8,ASR #2] //stores the least significant byte from
//r0 to a byte at an address equal to
//contents(r3) minus contents(r9)/4.
//r3 and r8 are not altered.
STR r5,[r7],#-8 //stores a word from r5 to the address
//in r7, and then decrements r7 by 8.
LDR r0,localdata //loads a word located at label localdata
2.一般数据处理指令
ADD SUB ADC SBC
AND, ORR, EOR,
CMP TST
UMULL, UMLAL, SMULL, and SMLAL
MUL, MLA, and MLS
ADC
Add with Carry.
Syntax ADC{cond}{S} Rd, Rn, Op2
Description Add Rn and Op2 and Carry flag and store result to Rd. ADC is typical used for multi-word arithmetic.
Condition Flags If S is specified update flags: N, Z, C, V.
Example
ADDS R0,R2,R4 // add R2 + R4, store result to R0, set flags
ADC R1,R3,R5 // add R3 + R5 with carry from previous ADDS, store result to R1
ADD
Add values and store result to register.
Syntax ADD{cond}{S} Rd, Rn, Op2
Description Add Rn and Op2 and store result to Rd.
Condition Flags If S is specified update flags: N, Z, C, V.
Example
ADDS R0,R2,R4 //Add R2 and R4 and store result to R0, update flags ADD R4,R4,#0xFF00 //Add value in 0xFF00 and R4 and store result in R4
SUB
Subtract registers.
Syntax SUB{cond}{S} Rd, Rn, Op2
Description subtracts the value of Op2 from the value in Rn.
Condition Flags If S is specified update flags: N, Z, C, V.
Example SUBS R8,R6,#240 //R8=R6-240
SBC
Subtract with carry.
Syntax SBC{cond}{S} Rd, Rn, Op2
Description synthesize multiword arithmetic.
Condition Flags If S is specified update flags: N, Z, C, V.
Example ADDS R0,R2,R4
ADD R4,R4,#0xFF00
AND
Logical AND operation.
Syntax AND{cond}{S} Rd, Rn, Op2
Description Load Rd with logical AND of Rn with Op2. Rd := Rn AND
Op2
Condition Flags If S is specified, N, Z flags are updated. C flag may be updated by calculation of Op2.
Example
AND R9,R2,#0xFF00 // Load R9 with R2 and value in 0xFF00
ORR
Logical OR operation.
Syntax ORR{cond}{S} Rd, Rn, Op2
Description OR operations on the values in Rn and Op2.
Condition Flags If S is specified, N, Z flags are updated. C flag may be updated by calculation of Op2.
Example ORR R2, R0, R5 // Rd = R0 or R5
CMP
Compare. Used in combination with conditional branch instructions. Syntax CMP {cond} Rn, Op2
Description subtracts the value of Op2 from the value in Rn (equals to the SUBS instruction with a discarded result).
This instruction updates the condition flags, but do not place a result in a register.
Condition Flags N, Z, C and V flags are updated.
Example CMP R2, R9 //Subtract value of R9 from R2
TST
Test.
Syntax TST{cond} Rn, Op2
Description performs a bitwise AND operation on the value in Rn and the value of Op2. This is similar to the ANDS instruction, except that the result is discarded.
Condition Flags N and Z flags are updated according the result. C flag may be updated during the calculation of Op2.
Example TSTNE r1,r5,ASR r1
MUL
Multiply (32-bit by 32-bit, bottom 32-bit result).
Syntax MUL{cond}{S} Rd, Rm, Rs
Description multiplies the values from Rm and Rs, and places the least significant 32 bits of the result in Rd.
Condition Flags If S is specified:
N and Z flags according to the result.
the C flag in ARM architecture v4 and earlier will be corrupted.
the C flag in ARM architecture v5 and later is not affected. Example MUL R10, R2, R5 //R10:= R2*R5
3.分支控制指令
B, BL, BX, BLX, and BXJ
B
Branch to label. Used to jump to a specific program location.
Syntax B{cond} label
Description The jump distance must be within -252 to +258 bytes for conditional and ±2 KBytes for unconditional branch.
Condition Flags not modified.
Example CMP R1,#10 // compare R10 with #10
BEQ val_ok // jump to label val_ok
val_ok:
val_err:
B val_err // jump to itself (loop forever)
BL
Branch with Link. Use to call subroutines.
Syntax BL{cond} label
Description Copy address of next instruction to R14 and jump to label. The jump distance must be within ±4Mb of the current instruction. Note that this mnemonic is generated as two 16-bit Thumb instructions.
Condition Flags not modified.
Example BL sub+ROM //Call subroutine at computed address ADDS R1,#1 //Add 1 to register 1, setting CPSR flags on the result then call subroutine if the C flag is clear, wich will be the case
//unless R1 held 0xFFFFFFFF
BX
Branch indirect and switch CPU mode (Thumb / ARM) as required. Syntax BX{cond} Rm
Description Branch to address in Rm. Change to ARM mode if bit 0 of Rm is clear.
Condition Flags not modified.
Example BX R5 // branch indirect to address function
4.ARM伪指令
1.符号定义伪指令
GBLA, GBLL, and GBLS
LCLA, LCLL, and LCLS
2.数据定义伪指令
DCB
DCD and DCDU
5.条件代码
Condition Code
Most ARM instructions and the Thumb Branch instruction include a condition code field. This field is marked in the CPU instructions with {cond}.
A conditional instruction is only executed on match of the condition flags in the Program Status Register. For example, the BEQ (
B instruction with EQ condition) branches only if the Z flag is set. If the {cond} field is empty the instruction is always executed.
{cond} Suffix Tested Status Flags Description
EQ Z set equal
NE Z clear not equal
CS/HS C set unsigned higher or
same
CC/LO C clear unsigned lower
MI N set negative
PL N clear positive or zero
VS V set overflow
VC V clear no overflow
HI C set and Z clear unsigned higher
LS C clear or Z set unsigned lower or same GE N equals V signed greater or equal LT N not equal to V signed less than
GT Z clear AND (N equals
V)
signed greater than
LE Z set OR (N not equal to
V)signed less than or equal
AL(ignored)always (usually
omitted)
Examples:
CMP R5,#10 // compare R5 with 10
BHI lab1 // branch to lab1 if value in R5 is higher than 10
:
lab1:
TST R5,#10 // test content of R5 against 10
ADDEQ R6,#40 // add 40 to R6 if R5 contains 10
6.移位类型
The ARM CPU has very powerful shift operations that can be used together with standard CPU instructions. The various shift types are explained below: Logical Shift Right (LSR)
Logical shift right is encoded with LSR #n or LSR Rs in the Op2 field. The value 0 is shifted into bit 31 and the Carry flag (C) holds the last bit shifted out.
Logical Shift Left (LSL)
Logical shift left is encoded with LSL #n or LSL Rs in the Op2 field. The value 0 is shifted into bit 0 and the Carry flag (C) holds the last bit shifted out.
Arithmetic Shift Right (ASR)
Arithmetic shift right is encoded with ASR #n or ASR Rs in the Op2 field. The sign bit (bit 31 of value) is shifted into the high bit 31 and the Carry flag (C) holds the last bit shifted out.
Rotate Right (ROR)
Rotate right is encoded with ROR #n in the Op2 field. Bit 0 of the value is shifted into bit 31. The Carry flag (C) holds the last bit shifted out.
Rotate Right Extended (RRX)
Rotate right extended is encoded with RRX in the Op2 field. The value of the Carry flag (C) is shifted into bit 31. The shifted out bit 0 is written to C.
Binary operators
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Assembler Guide
Home> Assembler Reference> Expressions, literals, and operators > Binary operators
Binary operators are written between the pair of subexpressions they operate on.
Binary operators have lower precedence than unary operators. Binary operators appear in this section in order of precedence.
Note
The order of precedence is not the same as in C, see Operator precedence in armasm and C.
Multiplicative operators
Multiplicative operators have the highest precedence of all binary operators. They act only on numeric expressions.
Table 3.9 shows the multiplicative operators.
Table 3.9. Multiplicative operators
OperatorAliasUsage Explanation
*A*B Multiply
/A/B Divide
:MOD:%A:MOD:BA modulo B
String manipulation operators
Table 3.10 shows the string manipulation operators. In CC, both A and B must be strings. In the slicing operators LEFT and RIGHT:
A must be a string
B must be a numeric expression.
Table 3.10. String manipulation operators
OperatorUsage Explanation
:CC:A:CC:B B concatenated onto
the end of A
:LEFT:A:LEFT:B The left-most B
characters of A
:RIGHT:A:RIGHT:BThe right-most B
characters of A
Shift operators
Shift operators act on numeric expressions, shifting or rotating the first operand by the amount specified by the second.
Table 3.11 shows the shift operators.
Table 3.11. Shift operators
OperatorAlias Usage Explanation
:ROL:A:ROL:BRotate A left by
B bits
:ROR:A:ROR:BRotate A right
by B bits