FPGA引脚

# clock pin for Basys Board
NET "CLK1" LOC = "p54"; # Bank = 2, Signal name = CLK1
NET "CLK2" LOC = "p53"; # Bank = 2, Signal name = CLK1

# Pin assignment for DispCtl
# Connected to Basys onBoard 7seg display

NET "seg<0>" LOC = "p25"; # Bank = 3, Signal name = CA
NET "seg<1>" LOC = "p16"; # Bank = 3, Signal name = CB
NET "seg<2>" LOC = "p23"; # Bank = 3, Signal name = CC
NET "seg<3>" LOC = "p21"; # Bank = 3, Signal name = CD
NET "seg<4>" LOC = "p20"; # Bank = 3, Signal name = CE
NET "seg<5>" LOC = "p17"; # Bank = 3, Signal name = CF
NET "seg<6>" LOC = "p83"; # Bank = 1, Signal name = CG
NET "dp" LOC = "p22"; # Bank = 3, Signal name = DP

NET "an<3>" LOC = "p26"; # Bank = 3, Signal name = AN3
NET "an<2>" LOC = "p32"; # Bank = 3, Signal name = AN2
NET "an<1>" LOC = "p33"; # Bank = 3, Signal name = AN1
NET "an<0>" LOC = "p34"; # Bank = 3, Signal name = AN0

# Pin assignment for LEDs
NET "Led<7>" LOC = "p2" ; # Bank = 3, Signal name = LD7
NET "Led<6>" LOC = "p3" ; # Bank = 3, Signal name = LD6
NET "Led<5>" LOC = "p4" ; # Bank = 3, Signal name = LD5
NET "Led<4>" LOC = "p5" ; # Bank = 3, Signal name = LD4
NET "Led<3>" LOC = "p7" ; # Bank = 3, Signal name = LD3
NET "Led<2>" LOC = "p8" ; # Bank = 3, Signal name = LD2
NET "Led<1>" LOC = "p14" ; # Bank = 3, Signal name = LD1
NET "Led<0>" LOC = "p15" ; # Bank = 3, Signal name = LD0

# Pin assignment for SWs
NET "sw<7>" LOC = "p6"; # Bank = 3, Signal name = SW7
NET "sw<6>" LOC = "p10"; # Bank = 3, Signal name = SW6
NET "sw<5>" LOC = "p12"; # Bank = 3, Signal name = SW5
NET "sw<4>" LOC = "p18"; # Bank = 3, Signal name = SW4
NET "sw<3>" LOC = "p24"; # Bank = 3, Signal name = SW3
NET "sw<2>" LOC = "p29"; # Bank = 3, Signal name = SW2
NET "sw<1>" LOC = "p36"; # Bank = 3, Signal name = SW1
NET "sw<0>" LOC = "p38"; # Bank = 2, Signal name = SW0

# Pin assignment for BTNs
NET "btn<3>" LOC = "p41"; # Bank = 2, Signal name = BTN3
NET "btn<2>" LOC = "p47"; # Bank = 2, Signal name = BTN2
NET "btn<1>" LOC = "p48"; # Bank = 2, Signal name = BTN1
NET "btn<0>" LOC = "p69"; # Bank = 2, Signal name = BTN0

# Loop back/demo signals
# Pin assignment for PS2
NET "PS2C" LOC = "p96" | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = PS2C
NET "PS2D" LOC = "p97" | DRIVE = 2 | PULLUP ; # Bank = 1, Signal name = PS2D
# Pin assignment for VGA
NET "HSYNC" LOC = "p39" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = HSYNC
NET "VSYNC" LOC = "p35" | DRIVE = 2 | PULLUP ; # Bank = 3, Signal name = VSYNC
NET "vgaRed<2>" LOC = "p67" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = RED2
NET "vgaRed<1>" LOC = "p68" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = RED1
NET "vgaRed<0>" LOC = "p70" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = RED0
NET "vgaGreen<2>" LOC = "p50" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = GRN2
NET "vgaGreen<1>" LOC = "p51" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = GRN1
NET "vgaGreen<0>" LOC = "p52" | DRIVE

= 2 | PULLUP ; # Bank = 2, Signal name = GRN0
NET "vgaBlue<1>" LOC = "p43" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = BLU2
NET "vgaBlue<0>" LOC = "p44" | DRIVE = 2 | PULLUP ; # Bank = 2, Signal name = BLU1