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DMOS

Application Note

AN-D15 The following outline explains how to read and use Supertex

MOSFET data sheets. The approach is simple and care has

been taken to avoid getting lost in a maze of technical jargon.

The VN3205 data sheet was chosen as an example because it

has the largest choice of packages. The product nomenclature

shown applies only to Supertex proprietary products.

Advanced DMOS Technology

This enhancement-mode (normally-off) DMOS FET transistors

utilize a vertical DMOS structure and Supertex’s well-proven

silicon-gate manufacturing process. This combination produces

devices with the power handling capabilities of bipolar transistors

and with the high input impedance and negative temperature

coefficient inherent in MOS devices. Characteristic of all MOS

structures, these devices are free from thermal runaway and

thermally-induced secondary breakdown.

Supertex vertical DMOS FETs are ideally suited to a wide range

of switching and amplifying applications where high breakdown

voltage, high input impedance, low input capacitance, and fast

switching speed are desired.

Maximum resistance from drain to

source when device is fully turned on

Drain to source breakdown voltage

& drain to gate breakdown voltage

Minimum drain current when

device is fully turned on

Understanding MOSFET Data

BV DSS/R DS(ON)I D(ON)

BV DGS(max)(min)SOT-89TO-92Quad P-DIP DIE

50V0.3? 3.0A VN3205N8VN3205N3VN3205N6VN3205ND

Order Number / Package

Ordering Information

This section outlines main features of the product

N-Channel Enhancement-Mode

Vertical DMOS FETs

Device Structure

V:Vertical DMOS (discretes & quads)

D:Vertical Depletion-Mode DMOS

discretes

T:Low threshold vertical DMOS

discretes

L:Lateral DMOS discretes

Type of Channel

?N-Channel, or

?P-Channel

Design

Supertex Family number

VN3205

Drain-to-Source Breakdown Voltage

divided by 10.

05:50V

11/12/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability

Package Options

?All Supertex devices can be stored and operated satisfactorily within these junction temperature (T J ) limits.?Appropriate derating factors from curves and change in parameters due to reduced/elevated temperatures have to be considered when temperature is not 25°C.?Operation at T J below maximum limit can enhance operating life.

V GS

?Most Supertex FETs are rated for ±20V

?± voltage handling capability allows quick turn off by reversing bias.?External protection should be used when there is a possibility of exceeding this rating. Stress exceeding ±20V will result in gate insulation degradation and eventual failure.

Maximum allowable temperature at leads while soldering,1.6mm away from case for 10 seconds.

Absolute Maximum Ratings

Drain-to Source Voltage BV DSS Drain-to-Gate

BV DGS Gate-to-Source Voltage

±20V

Operating and Storage Temperature -55°C to +150°C

Soldering Temperature

300°C

Ratings given in product summary.

Extreme conditions a device can be subjected to electrically and thermally. Stress in excess of these ratings will usually cause permanent damage.

Thermal Characteristics

Device characteristics affecting limits of heat produced and removed from device. Die size, R DS(ON) and packaging type are the main factors determining these thermal limitations.

The following DC parameters are 100% tested with 300μS, 2% duty cycle pulsed at 25°C, BV DSS , V GS(TH), I DSS , I D(ON) & R DS(ON).

??V GS(TH) and ?R DS(ON) are guaranteed by design ie., when device is functional for other DC parameters, these two parameters will not deviate from published values.?Since a representative sample is adequate to assure consistency of specs, A.C.parameters are sample tested on a lot/batch basis.

?High temperature testing on sample basis when requested with hi-rel processing.?Refer to section 3 “power MOS structures” for test circuits used for measurement.

?R DS(ON)

?Positive temperature coefficient.

?Enhances stability due to current sharing during parallel operation.R DS(ON)

?Drain to source resistance measured when device is partially turned on at V GS = 4.5V, and fully turned on at V GS = 10V.?Designers should use maximum values for worst case condition.?When better turn on characteristics (ie., low R DS(ON)) is required for logic level inputs, Supertex’s low threshold TN & TP devices may be used.

?Typical value of R DS(ON) can be calculated at various V GS conditions by using output characteristics or saturation characteristics family of curves (I D vs. V DS ).

?R DS(ON) increases with higher drain currents. R DS(ON) curve has a slight slope for low values of I D , but rises rapidly for high values.I D(ON)

?Defined as the minimum drain current when device is turned on.?Supertex measures I D(ON) min. at V GS = 10V.

Although Supertex specifies a typical value of I D(ON), the designer should use minimum value as the worst case.

BV DSS

?Please see product summary (part I)?Positive temperature coefficient. See curve BV DSS vs. T J .V GS(TH)

?Voltage required from gate to source to turn on device to certain I D current value given in “condition” column.?I D measurement condition is low for small die and higher for larger die.

?V GS(TH)

?Threshold voltage reduces when

temperature increases and vice versa.?Value at temperature other than 25 °C can be determined by V GS(TH)(normalized) vs. T J curve.I GSS

?Since the gate is insulated from the rest of device by a silicon dioxide insulating layer, this parameter depends on thick-ness/integrity of layer and size of device.?Measured at maximum permissible voltage from gate to source: ±20V.?Values of this parameter are often tens/hundreds of times less than published maximum value. Electrical screening is done at 100nA since test equipment

functions slowly at lower values, which is not practical for mass production. Con-sult factory for screening lower values.I DSS

?This is the leakage current from drain to source when device is fully turned off.?Measured by applying maximum

permissible voltage between drain and source (BV DSS ) and gate shorted to source (V GS = 0)

?Special electrical screening possible at lower values since max. published values are higher to achieve practical testing speeds.

Symbol Parameter

Min Typ

Max

Unit Conditions BV DSS Drain-to-Source Breakdown Voltage 50V V GS = 0V, I D = 10mA V GS(th)Gate Threshold Voltage

0.8

2.4V V GS = V DS , I D = 10mA ?V GS(th)Change in V GS(th) with Temperature -4.3-5.5mV/°C V GS = V DS , I D = 10mA I GSS Gate Body Leakage

1.0

100nA V GS = ±20V, V DS = 0V I DSS

Zero Gate Voltage Drain Current

10μA V GS = 0V, V DS = Max Rating 1

mA V GS = 0V, V DS = 0.8 Max Rating T A = 125°C

I D(ON)ON-State Drain Current

3.0

A V GS = 10V, V DS = 5V R DS(ON)

TO-92 and P-DIP 0.45?V GS = 4.5V, I D = 1.5A SOT-89

0.45?V GS = 4.5V, I D = 0.75A TO-92 and P-DIP 0.3?V GS = 10V, I D = 3A SOT-89

0.3?V GS = 10V, I D = 1.5A ?R DS(ON)Change in R DS(ON) with Temperature 0.85 1.2

%/°C V GS = 10V, I D = 3A G FS Forward Transconductance 1.0

1.5V DS = 25V, I D = 2A C ISS Input Capacitance

220300C OSS Common Source Output Capacitance 70120pF

V GS = 0V, V DS = 25V C RSS Reverse Transfer Capacitance 20

30 f = 1 MHz

t d(ON)Turn-ON Delay Time 10t r

Rise Time

15ns

t d(OFF)Turn-OFF Delay Time 25t f Fall Time

25V SD Diode Forward Voltage Drop 1.6

V V GS = 0V, I SD = 1.5A t rr

Reverse Recovery Time

300

V GS = 0V, I SD = 1A

Electrical Characteristics (@ 25°C unless otherwise specified)

V DD = 25V I D = 2A

R GEN = 10?

Switching Characteristics (continued)

t d(OFF)

?The sequence of events now begins to reverse. C ISS discharges through R GEN . The rise of V DS is initially slowed by increase of output capacitance.

t RR

?The reverse recovery time is the time needed for the carrier

gradient, formed during forward biasing, to be depleted when the biasing is reversed.?An external fast recovery diode may be connected from drain to source to improve recovery time.

V SD

?This is the forward voltage drop of the parasitic diode between drain and source.?Diode my be used as a commutator in H bridge configurations

or in a synchronous rectifier mode. Excessive fly back voltages may be clamped by this diode in a totem pole configuration.

t f

?V DS rises as the load resistor charges the output capacitance.

t r

?When C ISS is driven to a voltage exceeding V GS(TH), conduction from drain source begins. G FS increases causing increase in C ISS due to “Miller Effect” Charge requirements to Region II increase considerably. Gain stabilizes in Region III and “Miller Effect” is nullified, resulting in a linear change in V GS for increase in Q G .