PDU54-1500中文资料

4-BIT, ECL-INTERFACED

PROGRAMMABLE DELAY LINE (SERIES PDU54)

FEATURES

PACKAGES

? Digitally programmable in 16 delay steps ? Monotonic delay-versus-address variation ? Precise and stable delays

? Input & outputs fully 100K-ECL interfaced & buffered ? Available in 24-pin DIP (600 mil) socket or SMD

FUNCTIONAL DESCRIPTION

The PDU54-series device is a 4-bit digitally programmable delay line.The delay, TD A , from the input pin (IN) to the output pin (OUT) depends on the address code (A3-A0) according to the following formula:

TD A = TD 0 + T INC * A

where A is the address code, T INC is the incremental delay of the device, and TD 0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

? Total programmed delay tolerance: 5% or 40ps,

whichever is greater

? Inherent delay (TD 0):3.3ns typical ? Address to input setup (T AIS ): 2.9ns ? Operating temperature: 0° to 85° C

? Temperature coefficient: 100PPM/°C (excludes TD 0)? Supply voltage V EE : -5VDC ± 0.7V

? Power Supply Current: -300ma typical (50? to -2V)? Minimum pulse width: 3ns or 10% of total delay,

whichever is greater

? Minimum period: 8ns or 2 x pulse width, whichever

is greater

IN

OUT

Figure 1: Timing Diagram

?1997 Data Delay Devices

data delay devices, inc.

?3N/C N/C GND N/C N/C N/C N/C N/C GND OUT N/C N/C IN N/C VEE A3N/C N/C A2A1VEE A0N/C N/C

242322212019181716151413

123456789101112

N/C N/C GND N/C N/C N/C N/C N/C GND OUT N/C N/C

IN N/C VEE A3N/C N/C A2A1VEE A0N/C N/C

PDU54-xx DIP

PDU54-xxM Military DIP

PDU54-xxMC4Mil SMD

PIN DESCRIPTIONS

IN Signal Input OUT Signal Output A3-A0Address Bits VEE -5 Volts GND

Ground

DASH NUMBER SPECIFICATIONS

Part Number Incremental Delay Per Step (ps)Total Delay Change (ns)

PDU54-100100 ± 50 1.50PDU54-200200 ± 60 3.00PDU54-250250 ± 60 3.75PDU54-400400 ± 80 6.00PDU54-500500 ± 1007.50PDU54-750750 ± 10011.25PDU54-10001000 ± 20015.00PDU54-12001200 ± 20018.00PDU54-15001500 ± 20022.50PDU54-20002000 ± 40030.00PDU54-25002500 ± 40037.50PDU54-3000

3000 ± 500

45.00

NOTE:Any dash number between 100 and 3000

not shown is also available.

APPLICATION NOTES ADDRESS UPDATE

The PDU54 is a memory device. As such,

special precautions must be taken when

changing the delay address in order to prevent

spurious output signals. The timing restrictions

are shown in Figure 1.

After the last signal edge to be delayed has

appeared on the OUT pin, a minimum time,

T OAX, is required before the address lines can

change. This time is given by the following

relation:

T OAX = max { (A i - A i-1) * T INC , 0 }

where A i-1 and A i are the old and new address

codes, respectively. Violation of this constraint

may, depending on the history of the input signal,

cause spurious signals to appear on the OUT

pin. The possibility of spurious signals persists

until the required T OAX has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input

pulse width and period listed in the AC

Characteristics table. The recommended

conditions are those for which the delay

tolerance specifications and monotonicity are

guaranteed. The suggested conditions are

those for which signals will propagate through the

unit without significant distortion. The absolute

conditions are those for which the unit will

produce some type of output for a given input.

When operating the unit between the

recommended and absolute conditions, the

delays may deviate from their values at low

frequency. However, these deviations will

remain constant from pulse to pulse if the input

pulse width and period remain fixed. In other

words, the delay of the unit exhibits frequency

and pulse width dependence when operated

beyond the recommended conditions. Please

consult the technical staff at Data Delay Devices

if your application has specific high-frequency

requirements.

Please note that the increment tolerances listed

represent a design goal. Although most delay

increments will fall within tolerance, they are not

guaranteed throughout the address range of the

unit. Monotonicity is, however, guaranteed over

all addresses.

PACKAGE DIMENSIONS

PDU54-xx (Commercial DIP)

PDU54-xxM (Military DIP)

±.010

12345678

16151413

12

11

10

9

each .100±.010

Non-Accumulative

Lead Material:

Nickel-Iron alloy 42

TIN PLATE

20191817

24232221

PACKAGE DIMENSIONS (cont’d)

PDU54-xxC4 (Commercial SMD)PDU54-xxMC4 (Military SMD)

DEVICE SPECIFICATIONS

TABLE 1: AC CHARACTERISTICS

PARAMETER

SYMBOL MIN

TYP UNITS Total Programmable Delay TD T 7T INC Inherent Delay

TD 0 3.3

ns Address to Input Setup Time T AIS 2.9ns Output to Address Change

T OAX See Text Absolute

PER IN 20% of TD T Input Period Suggested

PER IN 40% of TD T Recommended PER IN 200% of TD T Absolute

PW IN 10% of TD T Input Pulse Width Suggested

PW IN 20% of TD T Recommended

PW IN

100

% of TD T

TABLE 2: ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Supply Voltage V EE -7.00.3V Input Pin Voltage V IN V EE - 0.30.3V Storage Temperature T STRG -65

150C Lead Temperature

T LEAD

300

C

10 sec

TABLE 3: DC ELECTRICAL CHARACTERISTICS

(0C to 85C)

PARAMETER

SYMBOL MIN MAX UNITS NOTES

High Level Output Voltage V OH -1.025-0.880V V IH = MAX,50? to -2V Low Level Output Voltage V OL -1.810-1.620V V IL = MIN, 50? to -2V

High Level Input Voltage V IH -1.165-0.880V Low Level Input Voltage V IL -1.810-1.475V High Level Input Current I IH 340

μA V IH = MAX Low Level Input Current

I IL

0.5

μA

V IL = MIN

DELAY LINE AUTOMATED TESTING

TEST CONDITIONS

INPUT:

OUTPUT:

Ambient Temperature:25o C ± 3o C Load:50? to -2V Supply Voltage (Vcc):-4.5V ± 0.1V C load :

5pf ± 10%Input Pulse:Standard 100K ECL

Threshold:

(V OH + V OL ) / 2levels

(Rising & Falling)

Source Impedance:50? Max.Rise/Fall Time: 1.0 ns Max. (measured

between 20% and 80%)

Pulse Width:PW IN = 10ns Period:PER IN = 100ns

NOTE:The above conditions are for test only and do not in any way restrict the operation of the device.

Test Setup

Timing Diagram For Testing

T RISE

T FALL

PER IN

PW IN

T RISE

T FALL

20%

20%

50%50%80%80%50%

50%

V IH

V IL

V OH

V OL

INPUT SIGNAL

OUTPUT SIGNAL