ICS501B中文资料

ICS501B LOCO? PLL C LOCK M ULTIPLIER

Description

The ICS501B LOCO TM is the most cost effective way to generate a high-quality clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 20 MHz.

Stored in the chip’s ROM is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies (see table on page 2).

The device also has an output enable pin which

tri-states the clock output when the OE pin is taken low. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. For applications which require defined input to output skew, use the ICS570B.Features

?Packaged as 8 pin SOIC or die ?Available in Pb (lead) free package ?ICS’ lowest cost PLL clock

?Zero ppm multiplication error

?Input crystal frequency of 5 MHz ?Input clock frequency of 5 MHz ?Output clock frequencies up to 15 MHz ?Extremely low jitter of 25 ps (one sigma)?Compatible with popular CPUs ?Duty cycle of 45/55 up to 20 MHz ?Nine selectable frequencies ?Operating voltage of 3.3 V or 5.5 V ?Tri-state output for board level testing ?25 mA drive capability at TTL levels ?Ideal for oscillator replacement ?Industrial temperature version available ?Advanced, low-power CMOS process

Block Diagram

Pin Assignment Clock Output Table

0 = connect directly to ground

1 = connect directly to VDD

M = leave unconnected (floating)

Pin Descriptions

S1S0

CLK

Minimum Input

04X input 0.5 MHz 0M 5.3125X input 1 MHz 015X input 0.5 MHz 5M 0 6.25X input 0.5 MHz M M 2X input 1 MHz M

1 3.125X input 1 MHz 106X input 0.5MHz 1M 3X input 0.5MHz 1

1

8X input

0.5MHz

Pin Number

Pin Name

Pin Type

Pin Description

1XI/ICLK Input Crystal connection or clock input.2VDD Power Connect to +3.3 V or +5 V .3GND Power Connect to ground.

4S1Tri-level Iinput

Select 1 for output clock. Connect to GND or VDD or float.5CLK Output Clock output per table above.

6S0Tri-level Input

Select 0 for output clock. Connect to GND or VDD or float.7OE Input Output enable. T ri-states CLK output when low. Internal pull-up.8

X2

Output

Crystal connection. Leave unconnected for clock input.

External Components

Decoupling Capacitor

As with any high-performance mixed-signal IC, the ICS501B must be isolated from system power supply noise to perform optimally.

A decoupling capacitor of 0.01μF must be connected between VDD and the GND. It must be connected close to the ICS501

B to minimize lead inductance. No external power supply filtering is required for the

ICS501B.

Series Termination Resistor

A 33? terminating resistor can be used next to the CLK pin for trace lengths over one inch. Crystal Load Capacitors

The total on-chip capacitance is approximately 12 pF. A parallel resonant, fundamental mode crystal should be used. The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground.

The value (in pF) of these crystal caps should equal (C L -12 pF)*2. In this equation, C L= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 8 pF [(16-12) x 2] = 8.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS501B. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Recommended Operation Conditions

DC Electrical Characteristics

VDD=5.0 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise

Item

Rating

Supply Voltage, VDD 7 V

All Inputs and Outputs

-0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Soldering Temperature

260°C

Parameter

Min.

Typ.Max.

Units

Ambient Operating Temperature

0+70°C Power Supply Voltage (measured in respect to GND)

+3.14

+5.25

V

Parameter

Symbol

Conditions

Min.

Typ.Max.

Units

Operating Voltage

VDD 3.14 5.25V Input High Voltage, ICLK only V IH ICLK (pin 1)(VDD/2)+1

V Input Low Voltage, ICLK only V IL ICLK (pin 1)(VDD/2)-1

V Input High Voltage V IH OE (pin 7) 2.0

V Input Low Voltage V IL OE (pin 7)0.8

V Input High Voltage V IH S0, S1VDD-0.5

V Input Low Voltage V IL S0, S10.5

V Output High Voltage V OH I OH = -25 mA 2.4

V Output Low Voltage

V OL

I OL = 25 mA 0.4

V IDD Operating Supply Current No load 20mA Short Circuit Current CLK output +70mA On-Chip Pull-up Resistor

Pin 7270k ?Input Capacitance, S1, S0, and OE Pins 4, 6, 7

4pF Nominal Output Impedance

20

?

AC Electrical Characteristics

VDD = 5.0 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise

Note 1: Measured with 15 pF load.

Parameter

Symbol

Conditions Min.

Typ.Max.

Units

Input Frequency, crystal input F IN 7.5MHz Input Frequency, clock input F IN 0.5

7.5MHz Output Frequency, VDD = 5.0 V ±5%F OUT 0°C to +70°C 415MHz -40°C to +85°C 415MHz Output Frequency, VDD = 3.3 V ±5%F OUT 0°C to +70°C 415MHz -40°C to +85°C 4

15

MHz Output Clock Rise Time t OR 0.8 to 2.0 V , Note 11ns Output Clock Fall Time t OF 2.0 to 8.0 V , Note 11

ns

Output Clock Duty Cycle t OD

1.5 V, up to 25 MHz

4549-51

55%PLL Bandwidth

10

kHz Output Enable Time, OE high to

output on

50ns Output Disable Time, OE low to tri-state

50ns Absolute Clock Period Jitter t ja Deviation from mean, Note 1+70ps One Sigma Clock Period Jitter t js

Note 1

25

ps

Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)

Package dimensions are kept current with JEDEC Publication No. 95

Ordering Information

“LF” denotes Pb (lead) free package.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.

Part / Order Number

Marking

Shipping Packaging

Package

Temperature

ICS501BM 501BM Tubes 8-pin SOIC 0 to +70° C ICS501BMT 501BM Tape and Reel

8-pin SOIC 0 to +70° C ICS501BMI 501BMI Tubes 8-pin SOIC -40 to +85° C ICS501BMIT 501BMI Tape and Reel

8-pin SOIC -40 to +85° C ICS501BMLF 501BML Tubes 8-pin SOIC 0 to +70° C ICS501BMLFT 501BML Tape and Reel

8-pin SOIC 0 to +70° C ICS501BMILF 501BMIL Tubes 8-pin SOIC -40 to +85° C ICS501BMILFT 501BMIL

Tape and Reel

8-pin SOIC

-40 to +85° C ICS501-DWF -Die on uncut, probed wafers 0 to +70° C ICS501-DPK

-

Tested die in waffle pack

0 to +70° C