电子信息工程专业英语课文翻译(第3版)
电子信息工程专业英语教程第三版
译者：唐亦林
p32
In 1945 H. W. Bode presented a system for analyzing the stability of feedback systems by using graphical methods. Until this time, feedback analysis was done by multiplication and division, so calculation of transfer functions was a time consuming and laborious task. Remember, engineers did not have calculators or computers until the '70s. Bode presented a log technique that transformed the intensely mathematical process of calculating a feedback system's stability into graphical analysis that was simple and perceptive. Feedback system design was still complicated, but it no longer was an art dominated by a few electrical engineers kept in a small dark room. Any electrical engineer could use Bode's methods find the stability of a feedback circuit, so the application of feedback to machines began to grow. There really wasn't much call for electronic feedback design until computers and transducers become of age.
1945年HW伯德提出了一套系统方法，用图形化方法来分析反馈系统的稳定性。在此之前，反馈分析是通过乘法和除法完成的，所以传递函数的计算是一项费时和费力的任务。请记得工程师们在上个世纪70年代之前是没有计算机或者计算器的。伯德提出了一种日志技术，这种技术将计算反馈系统稳定性这种复杂的数学过程转换为简单和直观的图像分析。反馈系统的设计虽然还是很复杂，
但它不再是几个电气工程师待在一个小黑屋里的艺术了。任何电气工程师都可以使用伯德的方法找到一个反馈电路的稳定点，因此反馈电路在机器中的应用开始增加。直到计算机和传感器的时代到来之前，反馈电路的设计真的没有太多的要求。
p36
An integrator(Figure 5.1a) is the simplest filter mathematically, and it forms the building block for most modern integrated filters. Consider what we know intuitively about an integrator. If you apply a DC signal at the input (i.e. , zero frequency), the output will describe a linear ramp that grows in amplitude until limited by the power supplies. Ignoring that limitation, the response of an integrator at zero frequency is infinite, which means that it has a pole at zero frequency.
(A pole exists at any frequency for which the transfer function’s value becomes infinite.)
从数学公式上讲，积分器（见图2.1a）是最简单的滤波器；它是构成大多数现代集成滤波器的基本模块。我们怎么从直观上理解积分器呢？假设在输入端加上一个直流信号（频率为0），那么在输出端将会出现一个线性斜坡信号,其幅度一直增至电源电压。如果不考虑电源电压对输出信号的限制，积分器在零频率上的响应将是无穷大，这意味着它在零频率点上存在一个极点（在任何使传递函数为无穷大值的频率点上都存在一个极点）。
p38
While the complex frequency’s imaginary part (jw) helps describe
a response to AC signals, the real part (q) helps describe a circuit’s transient response. Looking at Figure 5.2b, we can therefore say something about the RC low-pass filter’s response. Looking at Figure 5.2b, we can therefore say something about the RC low-pass filter’s response as compared to that of the integrator. The low-pass filter’s transient response is more stable, because its pole is in the negative-real half of the complex plane. That is, the low-pass filter makes a decaying-exponential response to a step-function input; the integrator makes an infinite response. For the low-pass filter, pole positions further down the - axis mean a higher 0, a shorter time constant, and therefore a quicker transient response. Conversely, a pole closer to the j axis causes a longer transient response.
复频率的虚部有助于描述电路对交流信号的响应，而其实部有助于描述电路的瞬态响应。从图2.2b中可以看出，RC低通滤波器的响应和积分器之间的一些区别。低通滤波器的瞬态响应更加稳定，因为其极点位于复平面的左半部。即对于阶跃函数输入，滤波器的响应是衰减指数形式的；积分器的响应是无穷大的。对于低通滤波器而言，极点沿坐标轴离原点越远，意味着0越大，时间常数越短，瞬态响应越快。相反的情况是：极点离j坐标轴越近，瞬态响应越慢。p47
The converter is essentially a highly over-sampling 1-bit ADC (the comparator) followed by digital filtering and decimation to realize the processing gain. The effective performance of the converter is greatly
enhanced by the addition of circuitry to shape the quantization noise such that, instead of being uniformly spread throughout the 0 to fs/2 band, it is minimized in the band of interest (Figure 6.5).
这个转换器实质上是一个后跟数字滤波和抽取、高过采样率的1位模数转换器（即比较器），用来实现处理增益。通过另外增加一个噪声整形电路去整型量化噪声，该转换器的有效性能获得了极大的提高。噪声整形电路将原来在0~1/2sf频带内均匀分布的噪声最大限度地从有用频带中去除（见图6.5）。
p62
The buck converter is capable of kilowatts of output power, but suffers from one serious shortcoming which would occur if the power switch were to fail short-circuited, the input power source is connected directly to the load circuitry with usually produces catastrophic results. To avoid this situation, a crowbar is placed across the output. A crowbar is a latching SCR which is fired when the output is sensed as entering an overvoltage condition. The buck converter should only be used for board-level regulation.
降压变压器可以产生上千瓦的输出功率，但它有个致命的缺陷，当开关电源发生短路时，输入电源会直接连接到负载电路上，这会导致可怕的后果。为了避免这种情况，要在输出端加上一个断路器。这个电路是一个闭合的可控硅整流器，当输出端被检测到一个过高的电压时，它就被触发工作了。降压型变换器只适合于板级调节。
p70
Clock Driver Skew (Intrinsic Skew) is the amount of skew caused by the clock driver itself. There are two kinds of clock driver devices; buffer devices and PLL-based devices. Skew occurs on the output of the buffer devices because of the differences in propagation delay of the input signal through the device. A majority of this difference is attributed to differences in output loading. Skew in PLL-based devices can be very small, since a PLL-based device can be adjusted to compensate for differences in output loading.
时钟驱动器偏移（固有偏移）是由时钟驱动器自己引起的偏移。有两种类型的时钟驱动设备，缓存器件和基于锁相环的器件。偏移发生在缓冲器件的输出端，因为输入信号通过器件时，其传播延迟有差异。造成这种差异的主要原有是输出负载的不同。基于锁相环的器件的偏斜可以是非常小的，因为锁相环器件可以被调节，以补偿输出负载的差异。
p71
Why is skew important? In high-speed systems, clock skew forms an important component of timing margin. A skew of 1 ns is a significant portion of a 15-ns cycle time. If the timing budget does not allow for skew, it is highly likely that the system will perform unreliably.
为什么偏移这么重要？在高速系统中，时钟偏移是时序富裕量的重要组成部分。在一个以15纳秒为周期的时间里，1纳秒的偏移都是很显著的部分。如果时序预算不允许偏移，系统很可能无法稳定运行。
p75
In today's designs, with clock rates over 100 MHz and rise times commonly 1 nanosecond (ns) or less, designers cannot ignore the role interconnections play in a logic design. Interconnect effects can play a significant part in the timing and noise characteristics of a circuit. The faster clock rates and rise times increase both capacitive and inductive coupling effects, which makes crosstalk problems greater. They also mean shorter time for reflections to decay before the data is clocked and read, which decreases the maximum line length that can be used for unterminated systems. This all means that one of the major interconnect challenges is to ensure signal integrity as the high-speed pulses move along the total interconnect path, from device to PCB, through the PCB to the backplane, and on out to any network connections which may be present.
在当今的设计中，时钟速率都超过了100MHz，并且上升沿通常只有1纳秒或者更少，设计者不能忽视在逻辑设计中互连的重要性。互连的效果对于一个电路的时序和噪声特性都能够起到很显著的影响。更快的时钟速率和上升沿都将增加电容耦合及电感耦合效应，这使得串扰问题更加严重。这也意味着在数据被写入和读取之前的反射衰减时间更短，它减少了无终端系统中最大的可用线路长度。这一切都意味着，主要的互连挑战之一是确保高速脉冲通过整个互连路径时的信号完整性，从器件到PCB板，再从PCB板到底板，最后到任何可能出现的网络连接。
p98
A third issue that has had a large impact on adoption is the widespread use of prepaid mobile phones in Europe (up to 75% in some areas). These can be purchased in many stores with no more formality than buying a radio. You pay and you go. They are preloaded with, for example, 20 or 50 euro and can be recharged when the balance drops to zero. As a consequence, practically every teenager and many small children in Europe have (usually prepaid) mobile phone so their parents can locate them, without the danger of the child running up a huge bill. If the mobile phone is used only occasionally, its use is essentially free since there is no monthly charge or charge for incoming calls.
被采纳的第三个已经产生很大影响的问题是，预付费移动电话在欧洲的广泛使用（有些地区达到了75%）。这些移动电话可以在许多商店里购买，购买手续不会比买一个收音机复杂。一手交钱，一手交货。这些电话被预充值了20或50欧元，当余额为0时，可以再充值。其结果是，几乎所有欧洲的少年和小孩子都持有移动电话（通常是预付费的），所以他们的家长可以找到他们，而不用承担孩子会欠巨额账单这样的风险。如果你只是偶尔使用移动电话，它用起来几乎是免费的，因为没有月租费，接听也不需要收费。
p107
An implicit assumption in our discussion is that the power levels of all stations are the same as perceived by the receiver. CDMA it typically used for wireless systems with a fixed base station and many
mobile stations at varying distances from it. The power levels received at the base station depend on how far away the transmitters are. A good heuristic here is for each mobile station to transmit to the base station at the inverse of the power level it receives from the base station. In other words, a mobile station receiving a weak signal from the base station will use more power than one getting a strong signal. The base station can also give explicit commands to the mobile stations to increase or decrease their transmission power.
在我们的讨论中隐含着一个假设是，所有基站的功率水平在接收器看来都是一样的。CDMA通常用于无线系统，系统中包含一个固定站和许多与它距离不同的移动站。基站收到的功率水平取决于发射机与它的距离。这里有一个很好的启发，对于每个移动站来说，它们所发射到基站的功率与它们从基站接收到的功率相反。换句话说，一个从基站收到弱信号的移动台，将比一个收到强信号的移动台发射更高的功率。基站还可以向移动台发送明确的指令，让它们增加或者减少其发射功率。
p113
The BIOS looks at the sequence of storage devices identified as boot devices in the CMOS Setup. "Boot" is short for "bootstrap", as in the old phrase "Lift yourself up by your bootstraps". Boot refers to the process of launching the operating system. The BIOS tries to initiate the boot sequence from the first device using the bootstrap loader.
BIOS查看一系列在CMOS设置中被确定为引导设备的存储设备。Boot是
bootstrap的缩写，就好像那句老话“通过你的靴带把你自己提起来。”Boot 指的是启动操作系统的过程。BIOS使用引导加载程序尝试在第一个设备中确定启动顺序。
p133
The design of a high-performance, full-custom integrated circuit (IC) is, of course, a difficult task. In full-custom IC design, everything, down to and including individual transistors may be designed (although libraries of parts are, of course, used). For many years, however, it has been possible to build semi-custom integrated circuits using gate arrays. A gate array, as its name suggests, is an integrated circuit on which an array of gates has been created. The design of an application-specific integrated circuit (ASIC) using a gate array therefore involves the definition of how the gates in the array should be connected. In practical terms, this means that one or two layers of metal interconnect must be designed. Since an integrated circuit requires seven or more processing stages, all the processing steps other than the final metalization can be completed in advance. Because the uncommitted gate arrays can be produced in volume, the cost of each device is relatively small.
高性能，全定制集成电路（IC）的设计当然是一个困难的任务。在全定制集成电路的设计中，所有事情，甚至是单个晶体管都需要被设计（当然，尽管要用
到一些库）。但是，多年以来，可以使用门阵列构建半导体集成电路。门阵列，正如其名，是由许多逻辑门所构建的集成电路。因此，使用门阵列进行专用集成电路的设计包括定义列阵中的逻辑门是如何连接的。在实际情况中，这意味着一到两层的金属互连必须被设计。由于集成电路需要七个或更多的加工过程，除了最终的金属化，其它步骤都可以预先完成。因为这些未知用途门列阵可以大量生产，每个器件的成本非常低。