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89C52_datasheet

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. ? Copyright 1998, Integrated Silicon Solution, Inc.

8-BIT MICROCONTROLLER with 8-Kbytes of FLASH

FEATURES

?80C51 based architecture

?8-Kbytes of on-chip Reprogrammable Flash Memory

?256 x 8 RAM

?Three 16-bit Timer/Counters ?Full duplex serial channel ?Boolean processor

?Four 8-bit I/O ports, 32 I/O lines ?Memory addressing capability – 64K ROM and 64K RAM ?Program memory lock – Lock bits (3)

? Power save modes:– Idle and power-down ?Eight interrupt sources

?Most instructions execute in 0.3 μs ?CMOS and TTL compatible

?Maximum speed: 40 MHz @ Vcc = 5V ?Industrial temperature available ?Packages available:– 40-pin DIP – 44-pin PLCC – 44-pin PQFP

GENERAL DESCRIPTION

The ISSI IS89C52 is a high-performance microcontroller fabricated using high-density CMOS technology. The CMOS IS89C52 is functionally compatible with the industry standard 80C51 microcontrollers.

The IS89C52 is designed with 8-Kbytes of Flash memory, 258 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; three 16-bit timer/counters;an eight-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS89C52 can be expanded using standard TTL compatible memory.

Figure 1. IS89C52 Pin Configuration: 40-pin PDIP

1234567891011121314151617181920

4039383736353433323130292827262524232221

T2/P1.0T2EX/P1.1

P1.2P1.3P1.4P1.5P1.6P1.7RST RxD/P3.0TxD/P3.1INT0/P3.2INT1/P3.3T0/P3.4T1/P3.5WR/P3.6RD/P3.7XTAL2XTAL1GND

VCC P0.0/AD0P0.1/AD1P0.2/AD2P0.3/AD3P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7EA/VPP ALE/PROG PSEN P2.7/A15P2.6/A14P2.5/A13P2.4/A12P2.3/A11P2.2/A10P2.1/A9P2.0/A8

IS89C52

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Figure 2. IS89C52 Pin Configuration: 44-pin PLCC

IS89C52ISSI?

Figure 3. IS89C52 Pin Configuration: 44-pin PQFP

IS89C52

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Figure 4. IS89C52 Block Diagram

IS89C52ISSI?Table 1. Detailed Pin Description

Symbol PDIP PLCC PQFP I/O Name and Function

ALE/PROG303327I/O Address Latch Enable: Output pulse for latching the low byte

of the address during an address to the external memory. In

normal operation, ALE is emitted at a constant rate of 1/6 the

oscillator frequency, and can be used for external timing or

clocking. Note that one ALE pulse is skipped during each

access to external data memory. This pin is also the Program

Pulse input (PROG) during Flash programming.

EA/V PP313529I External Access enable:EA must be externally held low to

enable the device to fetch code from external program memory

locations 0000H to FFFFH. If EA is held high, the device

executes from internal program memory unless the program

counter contains an address greater than 0FFFH. This also

receives the 12V programming enable voltage (V PP) during

Flash programming.

P0.0-P0.739-3243-3637-30I/O Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port

0 pins that have 1s written to them float and can be used as high-

impedance inputs. Port 0 is also the multiplexed low-order

address and data bus during accesses to external program and

data memory. In this application, it uses strong internal pullups

when emitting 1s.

Port 0 also receives the code bytes during programmable

memory programming and outputs the code bytes during

program verification. External pullups are required during pro-

gram verification.

P1.0-P1.71-82-940-44I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal

1-3pullups. Port 1 pins that have 1s written to them are pulled high

by the internal pullups and can be used as inputs. As inputs,

Port 1 pins that are externally pulled low will source current

because of the internal pullups. (See DC Characteristics: I IL).

The Port 1 output buffers can sink/source four TTL inputs.

Port 1 also receives the low-order address byte during Flash

programming and verification.

1240I T2(P1.0): Timer/Counter 2 external count input.

2341I T2EX(P1.1): Timer/Counter 2 trigger input.

P2.0-P2.721-2824-3118-25I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal

pullups. Port 2 pins that have 1s written to them are pulled high

by the internal pullups and can be used as inputs. As inputs,

Port 2 pins that are externally pulled low will source current

because of the internal pullups. (See DC Characteristics: I IL).

Port 2 emits the high order address byte during fetches from

external program memory and during accesses to external data

memory that used 16-bit addresses (MOVX @ DPTR). In this

application, Port 2uses strong internal pullups when emitting

1s. During accesses to external data memory that use 8-bit

addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of

the P2 Special Function Register.

Port 2 also receives the high-order bits and some control

signals during Flash programming and verification. P2.6 and

P2.7 are the control signals while the chip programs and

erases.

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Symbol PDIP PLCC PQFP I/O Name and Function

P3.0-P3.7

10-17

11, 13-19

5, 7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that have 1s written to them are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally pulled low will source current because of the internal pullups. (See DC Characteristics: I IL ).Port 3 also serves the special features of the IS89C52, as listed below:

10115I RxD (P3.0): Serial input port.11137O TxD (P3.1): Serial output port.12148I INT0 (P3.2): External interrupt 0.13159I INT1 (P3.3): External interrupt 1.141610I T0 (P3.4): Timer 0 external input.151711I T1 (P3.5): Timer 1 external input.

161812O WR (P3.6): External data memory write strobe.17

1913O RD (P3.7): External data memory read strobe.

PSEN

Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.

RST 9104I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal MOS resistor to GND permits a power-on reset using only an external capacitor connected to Vcc.

XTAL 1192115I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

XTAL 2182014O Crystal 2: Output from the inverting oscillator amplifier.GND 202216I Ground: 0V reference.

Vcc

Power Supply: This is the power supply voltage for operation.

Table 1. Detailed Pin Description (continued)

IS89C52ISSI?OPERATING DESCRIPTION

The detail description of the IS89C52 included in this description are:

? Memory Map and Registers

? Timer/Counters

? Serial Interface

? Interrupt System

? Other Information

? Flash Memory

MEMORY MAP AND REGISTERS

Memory

The IS89C52 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes long. The lower 8K program memory can reside on-chip. Figure 5 shows a map of the IS89C52 program and data memory.

The IS89C52 has 256 bytes of on-chip RAM, plus numbers of special function registers. The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. Figure 6 shows internal data memory organization and SFR Memory Map.

The lower 128 bytes of RAM can be divided into three segments as listed below and shown in Figure 7.

1.Register Banks 0-3: locations 00H through 1FH (32

bytes). The device after reset defaults to register bank

0. To use the other register banks, the user must select

them in software. Each register bank contains eight 1-byte registers R0-R7. Reset initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank.

2.Bit Addressable Area: 16 bytes have been assigned

for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this segment can also be addressed as a byte.

3.Scratch Pad Area: 30H-7FH are available to the user

as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction.

Figure 5. IS89C52 Program and Data Memory Structure

IS89C52

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SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFR's) are located in upper 128 Bytes direct addressing area. The SFR Memory Map in Figure 6 shows that.

Not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip. Read accesses to these addresses in general return random data, and write accesses have no effect.

User software should not write 1s to these unimplemented locations, since they may be used in future microcontrollers to invoke new features. In that case, the reset or inactive values of the new bits will always be 0, and their active values will be 1.

The functions of the SFRs are outlined in the following sections, and detailed in Table 2.

Accumulator (ACC)

ACC is the Accumulator register. The mnemonics for Accumulator-specific instructions, however, refer to the Accumulator simply as A.

B Register (B)

The B register is used during multiply and divide operations.For other instructions it can be treated as another scratch pad register.

Program Status Word (PSW). The PSW register contains program status information.

Figure 6. Internal Data Memory and SFR Memory Map

Figure 7. Lower 128 Bytes of Internal RAM

IS89C52ISSI?

SPECIAL FUNCTION REGISTERS

(Continued)

Stack Pointer (SP)

The Stack Pointer Register is eight bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. Data Pointer (DPTR)

The Data Pointer consists of a high byte (DPH) and a low byte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.

Ports 0 To 3

P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and 3, respectively.

Serial Data Buffer (SBUF)

The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer, where it is held for serial transmission. (Moving a byte to SBUF initiates the transmission.) When data is moved from SBUF, it comes from the receive buffer.Timer Registers

Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit Counter registers for Timer/Counters 0 and 1, respectively. Capture Registers

The register pair (RCAP2H, RCAP2L) are the Capture registers for the Timer 2 Capture Mode. In this mode, in response to a transition at the IS89C52's T2EX pin, TH2 and TL2 are copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value for this mode.

Control Registers

Special Function Registers IP, IE, TMOD, TCON, SCON, and PCON contain control and status bits for the interrupt system, the Timer/Counters, and the serial port. They are described in later sections of this chapter.

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Table 2. Special Function Registers Symbol Description

Direct Address

Bit Address, Symbol, or Alternative Port Function Reset Value ACC (1)Accumulator E0H E7E6E5E4E3E2E1E000H B (1) B register

F0H F7

00H DPH Data pointer (DPTR) high 83H 00H DPL Data pointer (DPTR) low

82H 00H AF AE AD AC AB AA A9A8IE

(1)

Interrupt enable A8H EA ——ES ET1EX1ET0EX00XX00000B BF BE BD BC BB BA B9B8IP (1)Interrupt priority

B8H ———PS PT1PX1PT0PX0XXX00000B

8786858483828180P0(1)

Port 0

80H

P0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0FFH

AD7AD6AD5AD4AD3AD2AD1AD09796959493929190P1(1)Port 190H P1.7P1.6P1.5P1.4P1.3P1.2P1.1P1.0FFH A7A6A5A4A3A2A1A0P2(1)

Port 2

A0H

P2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0FFH

AD15AD14AD13AD12AD11AD10AD9AD8B7B6B5B4B3B2B1B0P3(1)Port 3B0H P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0FFH RD WR T1T0INT1INT0TXD RXD PCON Power control 87H SMOD ———GF1GF0PD IDL 0XXX0000B D7D6D5D4D3D2D1D0PSW (1)Program status word D0H CY AC F0RS1RS0OV —P 00H SBUF Serial data buffer 99H XXXXXXXXB

9F 9E 9D 9C 9B 9A 9998SCON (1)

Serial controller 98H SM0

SM1

SM2REN

TB8

RB8TI RI 00H SP

Stack pointer 81H 07H 8F 8E 8D 8C 8B 8A 8988TCON (1)Timer control 88H TF1TR1TF0TR0IE1IT1IE0IT000H TMOD Timer mode 89H GATE C/T M1

M0GATE

C/T

00H TH0Timer high 08CH 00H TH1Timer high 18DH 00H TL0Timer low 08AH 00H TL1

Timer low 18BH 00H RCAP2H (2)Capture high CAH 00H RCAP2L (2)Capture low CBH 00H TL2(2)

Timer low 2

CCH

00H

Notes:

1. Denotes bit addressable.

2. SFRs are added to the 80C51 SFRs.

IS89C52ISSI?The detail description of each bit is as follows:

PSW:

Program Status Word. Bit Addressable.

76543210

CY AC F0RS1RS0OV—P Register Description:

CY PSW.7Carry flag.

AC PSW.6Auxiliary carry flag.

F0PSW.5Flag 0 available to the user for g e n e r a l

purpose.

RS1PSW.4Register bank selector bit 1.(1)

RS0PSW.3Register bank selector bit 0.(1)

OV PSW.2Overflow flag.

—PSW.1Usable as a general purpose flag

P PSW.0Parity flag. Set/Clear by hardware each

instruction cycle to indicate an odd/even

number of “1” bits in the accumulator.

Note:

1.The value presented by RS0 and RS1 selects the corre-

sponding register bank.

RS1RS0Register Bank Address

00000H-07H

01108H-0FH

10210H-17H

11318H-1FH PCON:

Power Control Register. Not Bit Addressable. 76543210 SMOD———GF1GF0PD IDL Register Description:

SMOD Double baud rate bit. If Timer 1 is used to generate baud rate and SMOD=1, the baud rate is doubled

when the serial port is used in modes 1, 2, or 3.—Not implemented, reserve for future use.(1)—Not implemented, reserve for future use.(1)—Not implemented, reserve for future use.(1)

GF1General purpose flag bit.

GF0General purpose flag bit.

PD Power-down bit. Setting this bit activates power-down mode.

IDL Idle mode bit. Setting this bit activates idle mode.

If 1s are written to PD and IDL at the same time,

PD takes precedence.

Note:

1. User software should not write 1s to reserved bits. These

bits may be used in future products to invoke new features.IE:

Interrupt Enable Register. Bit Addressable. 76543210 EA——ES ET1EX1ET0EX0 Register Description:

EA IE.7Disable all interrupts. If EA=0, no

interrupt will be acknowledged. If EA=1,

each interrupt source is individually

enabled or disabled by setting or

clearing its enable bit.

—IE.6Not implemented, reserve for future

use.(5)

—IE.5Not implemented, reserve for future

use.(5)

ES IE.4Enable or disable the serial port

interrupt.

ET1IE.3Enable or disable the Timer 1 overflow

interrupt.

EX1IE.2Enable or disable External Interrupt 1. ET0IE.1Enable or disable the Timer 0 overflow

interrupt.

EX0IE.0Enable or disable External Interrupt 0.

Note: To use any of the interrupts in the 80C51 Family, the following three steps must be taken:

1. Set the EA (enable all) bit in the IE register to 1.

2. Set the coresponding individual interrupt enable bit in

the IE register to 1.

3. Begin the interrupt service routine at the corresponding

Vector Address of that interrupt (see below).

Interrupt Source Vector Address

IE00003H

TF0000BH

IE10013H

TF1001BH

RI & TI0023H

4. In addition, for external interrupts, pins INT0 and INT1

(P3.2 and P3.3) must be set to 1, and depending on

whether the interrupt is to be level or transition acti-

vated, bits IT0 or IT1 in the TCON register may need to

be set to 0 or 1.

ITX = 0 level activated (X = 0, 1)

ITX = 1 transition activated

https://www.sodocs.net/doc/747220669.html,er software should not write 1s to reserved bits. These

bits may be used in future products to invoke new

features.

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IP:

Interrupt Priority Register. Bit Addressable.76543210—

—

PT1

PX1

PT0PX0

Register Description:—IP.7Not implemented, reserve for future use (3)—IP.6Not implemented, reserve for future use (3)—IP.5Not implemented, reserve for future use (3)PS IP.4Defines Serial Port interrupt priority level PT1IP.3Defines Timer 1 interrupt priority level PX1IP.2Defines External Interrupt 1 priority level PT0IP.1Defines Timer 0 interrupt priority level PX0IP.0Defines External Interrupt 0 priority level

Notes:

1.In order to assign higher priority to an interrupt the

coresponding bit in the IP register must be set to 1. While an interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt.

2.Priority within level is only to resolve simultaneous requests of the same priority level. From high-to-low,interrupt sources are listed below:IE0TF0IE1TF1RI or TI

TF2 or EXF2

https://www.sodocs.net/doc/747220669.html,er software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.

TCON:

Timer/Counter Control Register. Bit Addressable 76543210TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TF1TCON.7Timer 1 overflow flag. Set by hardware

when the Timer/Counter 1 overflows.Cleared by hardware as processor vectors to the interrupt service routine.

TR1TCON.6Timer 1 run control bit. Set/Cleared by

software to turn Timer/Counter 1 ON/OFF.

TF0TCON.5Timer 0 overflow flag. Set by hardware

when the Timer/Counter 0 overflows.Cleared by hardware as processor vectors to the interrupt service routine.

TR0TCON.4Timer 0 run control bit. Set/Cleared by

software to turn Timer/Counter 0 ON/OFF.

IE1TCON.3External Interrupt 1 edge flag. Set by

hardware when the External Interrupt edge is detected. Cleared by hardware when interrupt is processed.

IT1TCON.2Interrupt 1 type control bit. Set/Cleared

by software specify falling edge/low level triggered External Interrupt.

IE0TCON.1External Interrupt 0 edge flag. Set by

hardware when the External Interrupt edge is detected. Cleared by hardware when interrupt is processed.

IT0TCON.0Interrupt 0 type control bit. Set/Cleared

by software specify falling edge/low level triggered External Interrupt.

IS89C52ISSI?

TMOD:

Timer/Counter Mode Control Register.

Not Bit Addressable.

Timer 1 Timer 0

GATE C/T M1M0GATE C/T M1M0 GATE When TRx (in TCON) is set and GATE=1, TIMER/ COUNTERx will run only while INTx pin is high

(hardware control). When GATE=0, TIMER/

COUNTERx will run only while TRx=1 (software

control).

C/T Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set

for Counter operation (input from Tx input pin). M1Mode selector bit.(1)

M0Mode selector bit.(1)

Note 1:

M1M0Operating Mode

00Mode 0. (13-bit Timer)

01Mode 1. (16-bit Timer/Counter)

10Mode 2. (8-bit auto-load Timer/Counter)

11Mode 3. (Splits Timer 0 into TL0 and

TH0. TL0 is an 8-bit Timer/Counter

controller by the standard Timer 0

control bits. TH0 is an 8-bit Timer and

is controlled by Timer 1 control bits.) 11Mode 3. (Timer/Counter 1 stopped).SCON:

Serial Port Control Register. Bit Addressable. 76543210 SM0SM1SM2REN TB8RB8TI RI Register Description:

SM0SCON.7Serial port mode specifier.(1)

SM1SCON.6Serial port mode specifier.(1)

SM2SCON.5Enable the multiprocessor com-

munication feature in mode 2 and 3. In

mode 2 or 3, if SM2 is set to 1 then RI

will not be activated if the received 9th

data bit (RB8) is 0. In mode 1, if SM2=1

then RI will not be activated if valid stop

bit was not received. In mode 0, SM2

should be 0.

REN SCON.4Set/Cleared by software to Enable/

Disable reception.

TB8SCON.3The 9th bit that will be transmitted in

mode 2 and 3. Set/Cleared by software. RB8SCON.2In modes 2 and 3, RB8 is the 9th data

bit that was received. In mode 1, if

SM2=0, RB8 is the stop bit that was

received. In mode 0, RB8 is not used. TI SCON.1Transmit interrupt flag. Set by hardware

at the end of the eighth bit time in mode

0, or at the beginning of the stop bit in

the other modes. Must be cleared by

software.

RI SCON.0Receive interrupt flag. Set by hardware

at the end of the eighth bit time in mode

0, or halfway through the stop bit time

in the other modes (except see SM2).

Must be cleared by software.

Note 1:

SM0SM1MODE Description Baud Rate

000Shift register Fosc/12

0118-bit UART Variable

1029-bit UART Fosc/64 or

Fosc/32

1139-bit UART Variable

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T2CON:

Timer/Counter 2 Control Register. Bit Addressable.76543210TF2

EXF2RCLK TCLK EXEN2TR2C/T2CP/RL2

TF2T2CON.7Timer 2 overflow flag set by hardware

and cleared by software. TF2 cannot be set when either RCLK = 1 or TCLK = 1.

EXF2T2CON.6Timer 2 external flag set when either a

capture or reload is caused by a negative transition on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to vector to the Timer 2 interrupt routine.EXF2 must be cleared by software.

RCLK T2CON.5Receive clock flag. When set, causes

the Serial Port to use Timer 2 overflow pulses for its receive clock in modes 1and 3. RCLK = 0 causes Timer 1overflow to be used for the receive clock.

TLCK T2CON.4Transmit clock flag. When set, causes

the Serial Port to use Timer 2 overflow pulses for its transmit clock in modes 1and 3. TCLK = 0 causes Timer 1overflows to be used for the transmit clock.

EXEN2T2CON.3 Timer 2 external enable flag.

When set, allows a capture or reload to occur as a result of negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

TR2

T2CON.2Software START/STOP control for

Timer 2. A logic 1 starts the Timer.

C/T2T2CON.1Timer or Counter select.

0 = Internal Timer. 1 = External Event Counter (triggered by falling edge).

CP/RL2T2CON.0Capture/Reload flag.

When set, captures occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1.When either RCLK = 1 or TCLK = 1,this bit is ignored and the Timer is forced to auto-reload on Timer 2overflow.

Note:

1. Timer 2 Operating Modes RCLK + TCLK CP/RL2TR2

MODE

00116-Bit Auto-Reload 01116-Bit Capture 1X 1Baud Rate Generator X

(Off)

IS89C52ISSI?TIMER/COUNTERS

The IS89C52 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. All two can be configured to operate either as Timers or event Counters.

As a Timer, the register is incremented every machine cycle. Thus, the register counts machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

As a Counter, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 and T1. The external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but it should be held for at least one full machine cycle to ensure that a given level is sampled at least once before it changes.

In addition to the Timer or Counter functions, Timer 0 and Timer 1 have four operating modes: 13-bit timer, 16-bit timer, 8-bit auto-reload, split timer. Timer 2 in the IS89C52 has three modes of operation: Capture, Auto-Reoload, and Baud Rate Generator.Timer 0 and Timer 1

The Timer or Counter function is selected by control bits

C/T in the Special Function Regiser TMOD. These two

Timer/Counters have four operating modes, which are

selected by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2

are the same for both Timer/Counters, but Mode 3 is different.

The four modes are described in the following sections. Mode 0:

Both Timers in Mode 0 are 8-bit Counters with a divide-by-32

prescaler. Figure 8 shows the Mode 0 operation as it applies

to Timer 1.

In this mode, the Timer register is configured as a 13-bit

Timer interrupt flag TF1. The counted input is enabled to the

Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting

GATE = 1 allows the Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is a control bit in the Special Function Register TCON. Gate is in

TMOD.

The 13-bit register consists of all eight bits of TH1 and the

lower five bits of TL1. The upper three bits of TL1 are

indeterminate and should be ignored. Setting the run flag

(TR1) does not clear the registers.

Mode 0 operation is the same for Timer 0 as for Timer 1,

except that TR0, TF0 and INT0 replace the corresponding

Timer 1 signals in Figure 8. There are two different GATE

bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Figure 8. Timer/Counter 1 Mode 0: 13-Bit Counter

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Mode 1:

Mode 1 is the same as Mode 0, except that the Timer register is run with all 16 bits. The clock is applied to the combined high and low timer registers (TL1/TH1). As clock pulses are received, the timer counts up: 0000H, 0001H,0002H, etc. An overflow occurs on the FFFFH-to-0000H overflow flag. The timer continues to count. The overflow flag is the TF1 bit in TCON that is read or written by software (see Figure 9).

Mode 2:

Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure 10. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reload leaves the TH1 unchanged. Mode 2 operation is the same for Timer/Counter 0.

Mode 3:

Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 11. TL0 uses the Timer 0 control bits: C/T , GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt.

Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the IS89C52 can appear to have four Timer/Counters. When Timer 0 is in Mode 3,Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt.

Figure 10. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload

Figure 9. Timer/Counter 1 Mode 1: 16-Bit Counter

IS89C52ISSI?

Figure 11. Timer/Counter 0 Mode 3: Two 8-Bit Counters

Timer 2

This is a powerful addition to the other two just discussed. Five extra special function registers are added to accommodate Timer 2 which are: the timer registers, TL2 and TH2, the timer control register, T2CON, and the capture registers, RCAP2L and RCAP2H. Like Timers 0 and 1, it can operate either as a timer or as an event counter, depending on the value of bit C/T2 in the Special Function Register T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator, which are selected by RCLK, TCLK, CP/RL2, and TR2. In the Capture Mode, the EXEN2 bit in T2CON selects two options. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter whose overflow sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 performs the same way, but a 1-to-0 transition at external input T2EX also causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into the RCAP2L and RCAP2H registers, respectively. In addition, the transition at T2EX sets the EXF2 bit in T2CON, and EXF2, like TF2, can generate an interrupt.

The Capture Mode is illustrated in Figure 12.

In the auto-reload mode, the EXEN2 bit in T2CON also selects two options. If EXEN2 = 0, then when Timer 2 rolls over it sets TF2 and also reloads the Timer 2 registers with the 16-bit value in the RCAP2L and RCAP2H registers, which are preset by software. If EXEN2 = 1, then Timer 2 performs the same way, but a 1-to-0 transition at external input T2EX also triggers the 16-bit reload and sets EXF2. The auto-reload mode is illustrated in Figure 13.

The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. This mode is described in conjunction with the serial port (see Figure 14).

IS89C52

18Integrated Silicon Solution, Inc. — 1-800-379-4774

MC013-1C ISSI

Figure 13. Timer 2 in Auto-Reload Mode

Figure 14. Timer 2 in Baud Rate Generator Mode

Note:

T2EX can be used as an additional external interrupt.

Figure 12. Timer 2 In Capture Mode

IS89C52

ISSI

Table 5. Timer/Counter 1 Used as a Timer TMOD

Mode Timer 1

Internal External

Function Control (1)

Control (2)

013-Bit Timer 00H 80H 116-Bit Timer 10H 90H 28-Bit Auto-Reload 20H A0H 3

Does Not Run

30H

B0H

Table 6. Timer/Counter 1 Used as a Counter TMOD

Mode Timer 1

Internal External

Function Control (1)

Control (2)

013-Bit Timer 40H C0H 116-Bit Timer 50H D0H 28-Bit Auto-Reload 60H E0H 3

Not Available

—

Notes:

1.The Timer is turned ON/OFF by setting/clearing bit TR1in the software.

2.The Timer is turned ON/OFF by the 1-to-0 transition on INT1 (P

3.3) when TR1 = 1 (hardware control).

Timer Setup

Tables 3 through 6 give TMOD values that can be used to set up Timers in different modes.

It assumes that only one timer is used at a time. If Timers 0 and 1 must run simultaneously in any mode, the value in TMOD for Timer 0 must be ORed with the value shown for Timer 1 (Tables 5 and 6).

For example, if Timer 0 must run in Mode 1 GATE (external control), and Timer 1 must run in Mode 2 COUNTER, then the value that must be loaded into TMOD is 69H (09H from Table 3 ORed with 60H from Table 6).

Moreover, it is assumed that the user is not ready at this point to turn the timers on and will do so at another point in the program by setting bit TRx (in TCON) to 1.Table 3. Timer/Counter 0 Used as a Timer TMOD

Mode Timer 0Internal External

Function Control (1)

Control (2)

013-Bit Timer 00H 08H 116-Bit Timer 01H 09H 28-Bit Auto-Reload 02H 0AH 3

Two 8-Bit Timers

03H

0BH

Table 4. Timer/Counter 0 Used as a Counter TMOD

Mode Timer 0Internal External

Function Control (1)

Control (2)

013-Bit Timer 04H 0CH 116-Bit Timer 05H 0DH 28-Bit Auto-Reload 06H 0EH 3

One 8-Bit Counter

07H

0FH

Notes:

1.The Timer is turned ON/OFF by setting/clearing bit TR0in the software.

2.The Timer is turned ON/OFF by the 1 to 0 transition on INT0 (P

3.2) when TR0 = 1 (hardware control).

IS89C52

20Integrated Silicon Solution, Inc. — 1-800-379-4774

MC013-1C ISSI

SERIAL INTERFACE

The Serial port is full duplex, which means it can transmit and receive simultaneously. It is also receive-buffered,which means it can begin receiving a second byte before a previously received byte has been read from the receive register. (However, if the first byte still has not been read when reception of the second byte is complete, one of the bytes will be lost.) The serial port receive and transmit registers are both accessed at Special Function Register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register.

The serial port can operate in the following four modes:Mode 0:

Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmitted/received, with the LSB first. The baud rate is fixed at 1/12 the oscillator frequency (see Figure 15).

Mode 1:

Ten bits are transmitted (through TXD) or received (through RXD): a start bit (0), eight data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in Special Function Register SCON. The baud rate is variable (see Figure 16).

Mode 2:

Eleven bits are transmitted (through TXD) or received (through RXD): a start bit (0), eight data bits (LSB first), a programmable ninth data bit, and a stop bit (1). On transmit,the ninth data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) can be moved into TB8. On receive, the ninth data bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency (see Figure 17).

Mode 3:

Eleven bits are transmitted (through TXD) or received (through RXD): a start bit (0), eight data bits (LSB first), a programmable ninth data bit, and a stop bit (1). In fact,Mode 3 is the same as Mode 2 in all respects except the baud rate, which is variable in Mode 3 (see Figure 18).In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1.Reception is initiated in the other modes by the incoming start bit if REN = 1.

Timer/Counter 2 Set-Up

Except for the baud rate generator mode, the values given for T2C0N do not include the setting of the TR2 bit. Therefore,bit TR2 must be set separately to turn the Timer on.Table 7. Timer/Counter 2 Used as a Timer T2CON Mode

Internal External Control (1)Control (2)

16-Bit Auto-Reload 00H 08H 16-Bit Capture

01H 09H Baud Rate Generator Receive 34H 36H and Transmit Same Baud Rate Receive Only 24H 26H Transmit Only

14H

16H

Table 8. Timer/Counter 2 Used as a Counter TMOD

Mode

Internal External Control (1)Control (2)

16-Bit Auto-Reload 02H 0AH 16-Bit Capture

03H

0BH

Notes:

1.Capture/Reload occurs only on Timer/Counter overflow.

2.Capture/Reload occurs on Timer/Counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode.

89C52_datasheet

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