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题目宽频带频率计的设计

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An alternative method of precise frequency by the aid of a DDS 1 The proposed frequency measurement technique

The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a 33 MHz clock would effectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolution will depend on the number of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/ 2n ) becomes finer i.e. it improves. The impact of the clock frequency decrease is the subsequent decrease of its maximum output frequency that limits the counter's maximum count. The major blocks have been shown . Among them are the Frequency Comparator and the DDS. To overcome some disadvantages of the specific frequency comparator a correction stage has been incorporated. This stage is also used for the measurement extraction in order to display the correct reading.

1.1Operation of the circuit

The circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half of it's maximum. In addition, the frequency step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximation the frequency step is divided by two and added or subtracted to the FSW of the DDS, depending on the output of the Frequency Comparator. The approximation procedure stops when the step size decreases to one. After that, an

up/down counter substitutes the approximation mechanism. The digital FSW, after the appropriate correction and decoding, is presented in an output device i.e. an LCD display or any other suitable means. Alternatively, it can be digitally recorded or it can be read by a computer. As conclusion of this initial approach we could say that the proposed method is based on a Digital Controlled Synthesizer which is forced to produce a frequency almost equal to the unknown one.

1.2Frequency comparison

The frequency comparator seems to be the most critical stage of the design. The implementation is based on a modified phase/frequency comparator proposed by Philips in the 74HC4046 PLL device. It consists primarily of two binary counters, counting up to two and an RS flip-flop. The function of the frequency comparator is based on the principle that the lower frequency, i.e. larger period, includes (embraces) at least one or more full periods of the higher frequency (smaller period). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, the circuit operates as follows: When the first counter (#1) encounters two rising edges of the unknown frequency in one period of the DDS, it sets the output of the RS flip-flop. The logic "1" of the RSflip-flop acting at the U/D control input of the Up/Down counter forces the DDS to rise its output frequency. On the contrary, when the second counter (#2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flip-flop's output. This action decreases the frequency of the DDS. At a first glance one could think that the synthesized frequency could reach the measured one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as "hysteresis". Hysteresis depends on the initial timing relation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous i.e. it can be erroneous. The ambiguity settles when two rising edges of the higher frequency waveform occur during one period of the lower one. If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the comparator's output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition, because (as in a voltage comparator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situation is controlled, as will be explained later. Although an analog implementation of the frequency comparator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog components, wide frequency range of operation and shorter response time.

1.3Interaction between frequency comparator and digital

synthesizer

After the successive approximation of the unknown frequency the Frequency Comparator "realizes" that the synthesized frequency is higher (lower) than the unknown one and produces a

logic 0 (1) at the output which commands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the unknown one. This will not be "realized" by the frequency comparator and the synthesized frequency will keep on increasing for some clock cycles, until the comparator detects the correct relation of it's two input frequencies, the unknown one and the DDS output. The same phenomenon will be observed for the opposite (decreasing) case also. This is due to hysteresis that was mentioned earlier. When DDS output (fDDS) has approached fin, due to hysteresis, no specific frequency is synthesized. Instead, it swings between f1 and f2, where f1 and f2 are the two extreme values of the frequency swing lying symmetrically around fin. The DDS output can be considered as a frequency modulated carrier by a triangular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a typical output of the Frequency Comparator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has been captured using an auxiliary hardware circuit: A digital-to-analog converter (DAC) was connected to the output of the U/D counter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differently, the lower trace is the U/D command (input) to the counter while the upper trace is a hypothetical "frequency modulating" waveform. It is obvious that the term "hypothetical" is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope of the elements of the triangular waveform is constant for constant input frequency and depends on the clock of the U/D counter (horizontal axis) and the voltage reference of the DAC (vertical axis). This slope is ± k i fin .

1.4 Description of the prototype hardware

For evaluation purposes two prototypes have been built and tested in the laboratory. The first approach was a low frequency instrument (operating up to 15 KHz) . The purpose of this implementation was to study the principles of operation of the proposed method. Next, a higher frequency prototype was built which will be described in more detail here. In order to implement the digital part of the prototype, (Frequency Comparator, Successive Counter, Correction Stage) two PLD devices from Altera (EPF 8064LC68-12) were used. These devices are interconnected with

the DDS, which is the Q2240I-3S1 from Qualcomm. The DDS has a 32-bit input and

a 12-bit output for the sine lookup table (LUT). The 12-bit output of the LUT is fed into the D/A converter, the AD9713B from Analog Devices. Its analog output is connected to an I/V amplifier (current-to-voltage converter). The generated sinewave has upper harmonics, due to the DAC operation. These harmonics are removed from the filters that follow the DAC. The correction stage is implemented partially on the PLDs and partially on the microcontroller. Based on the up-down command of the frequency comparator we store the two extreme values, FSW1 and FSW2, which are then transferred into the micro-controller (Atmel AT89C52), transformed into numerical representation and fed to the LCD Display. The micro-controller also controls the whole operation of the prototype. The behaviour of the instrument was according to the expected and was alike to a conventional

bench frequency counter. The speed of measurement was checked using lower trace, obtained by the aid of a digital oscilloscope. Each state, high or low, of this waveform corresponds to the time required for one measurement.

1.1 电路的操作

该电路工作在这样的方式即一个新测量的 DDS 的输出频率会在开始以逐

次逼近的方法受到控制。初始 DDS 的频率将是它最大值的一半。此外，该步骤将频率近似等于 DDS 的最大频率的 1/ 4。根据比较器输出的频率，在每一个近似值中频率被分成两个并且增加或减少到 DDS 的 FSW 中。在步长下降到一定程度时逼近过程停止。在此之后，向上/向下计数器替代逼近机制。在适当的修正和解码后，数码的 FSW 被显示在一个输出设备中，即一台液晶显示器或任何其他合适的设备。或者，也可以进行数字记录，也可以由计算机阅读。作为这一初步方法的结论，我们可以说，该方法是基于数字控制合成的，这个数字合成器能被迫产生和未知频率几乎相等的频率。

1.2 频率比较

频率比较似乎是设计的最关键阶段。该实现是基于一种改进的相位/频率比较器，由飞利浦在 74HC4046 PLL 设备中生产。它主要包括两个二进制计数器和一个 RS 触发器。频率比较器的功能是基于较低频率，即较大的周期的原则，包括至少有一个或多个频率较高（小周期）的完整周期。这意味着，在较低频率周期内包含两个或两个以上的有较高频率上升边缘的波形。鉴于上述情况，电路操作如下：当第一个计数器（＃1）在一个时期内遇到 DDS 的两个未知频率的上升边缘，它设置 RS 触发器的输出。触发器的逻辑“1” 在向上/向下计数器的 U / D 的控制输出中起 RS 作用，强制 DDS 升高输出频率。相反，当第二个计数器（＃2）在一个周期内记录 DDS 输出的两个未知频率的上升边缘，它又恢复成 RS 触发器的输出。这个动作降低了 DDS 的频率。乍一看人们可能认为，合成频率可达到实测值，然后计数器停止运作。不幸的是并非如此。一个充满活力的机制代替了它。该电路需要一些时间来实现正确的频率关系。我们将把这个时间称为“迟滞” 。迟滞取决于最初的 DDS 输出时序关系和未知频率。最初，在滞后期，有关更大的频率的指示是不明确的，即它可能是错误的。当更高的频率上升边缘波形发生在较低的时期时将会产生歧义。当我们考虑 DDS 的频率等于未知频率之一时，我们会发现，比较器的输出将切换，说明 DDS 的频率高于或低于未知频率。这实际上是一个可以接受和预期的状况，因为一个相同的指示（如电压比较器）可能不存在。在我们的例子中，这不是一个问题，因为这个电路是嵌入在一个封闭的循环之中。该循环经过一段短暂的时间，迟滞等情况将得到扭转。滞后的时间是可变的。这种情况如何控制，也将在后面解释。虽然与模拟执行频率相比较将产生更大的噪音，我们仍坚持数字化的实现，原因有三：超大型电路或可编程逻辑器件（PLD）容易实现，不需要模拟组件，频率范围宽并且需要更短的响应时间。

1.3 频率比较器和数字频率合成器之间的相互作用

在频率比较器“实现” 的未知频率逐次逼近之后，合成的频率较高（低）于未知，并在控制向上/向下计数器的输出端产生向下(上)的一个逻辑 0（1）的方向。如前所述，这个计数器的输出被认为是从 FSW 到 DDS 的阶段。在最初的 DDS 频率降低时，合成频率将会逐步增加，达到未知频率之一。这不会通过频率比较器“实现”，合成频率将会在一些时钟周期内继续增加，直到比较器检测出它的两个输入即频率未知的一方和 DDS 输出的正确关系。在相反（降低）的情况下，同样的现象也将会被观察到。这是因为前面提到的滞后作用。当 DDS 输出（fDDS）已接近 fin，由于滞后性，没有特定的频率合成。相反，它摇摆于 F1 和 F2 之间，其中 F1 和 F2 是频率对称摆动的两个极端值。DDS 的输出可以被看作是一个三角波形调制载波频率。三角波形是 FSW 施加到 DDS 的模拟表示法。较低的跟踪显示一个比较典型的频率输出。在相同的图上跟踪，以模拟的形式显示 FSW 的变化，这是因为它企图接近正确的值。利用辅助硬件电路这个波形已被俘获：为了研究操作，输出数字至模拟转换器（DAC）连接到 U / D 转换计数器（最高位。该 DAC 没有显示电路框图。换句话说，较低水平的跟踪是将 U / D 命令（输入）到计数器上，而跟踪的痕迹是一个假设的“调频”波形。很明显，使用“假设”是因为在电路（除辅助 DAC）中没有一个可用的波形。相反，其相等数值存在。三角波形的坡度大小对于常数输入频率是恒定的，并且取决于 U/ D 转换计数器（水平轴）时钟和 DAC（垂直轴）的电压基准。这里的坡度为± k i fin 。

1.4 硬件原型的说明

用于评估的两个原型在实验室已建成并进行测试。第一种方法是用低频率仪器（工作达15千赫。这次实验实施的目的是研究该方法的操作原则。接下来，用一个更高频率的仪器原型，将在这里进行更详细的描述。为了使原型的数字部分（频率比较，连续计数器，校正阶段）生效，两个产自 Altera（EPF8064LC68 - 12）的 PLD 器件将被使用。这些设备和由高通 Q2240I - 3S1 所生产 DDS 相互联系。 DDS 具有 32 位输入和 12 位输出的正弦查找表（LUT）。送入到由模拟设备 AD9713B 发出的 D / A 转换器中。其模拟输出连接到 I / V 放大器（电流电压转换器）。由于DAC的工作，生成的正弦波具有较高的谐波。这些谐波在DAC 之后将从过滤器删除。这次调整阶段一部分实施在 PLD一部分在微控制器。基于频率比较器的上下命令，我们存储两个极端值，FSW1和FSW2，然后再进入微控制器（ Atmel AT89C52）转换成数字表示并反馈到 LCD 显示器。该微控制器还控制着整个运作的原型。仪器的行为和预期的一样，和常规的频率计数器工作台是一样的。在数字示波器的帮助下，测量采用较低速度跟踪检查。每个状态，波形的高或低，对应一个测量所需的时间。

英文文献翻译

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论文外文文献翻译3000字左右

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Economic policy,tourism trade and productive diversification （Excerpt） Iza Lejárraga,Peter Walkenhorst The broad lesson that can be inferred from the analysis is that promoting tourism linkages with the productive capabilities of a host country is a multi-faceted approach influenced by a variety of country conditions.Among these,fixed or semi-fixed factors of production,such as land,labor,or capital,seem to have a relatively minor influence.Within the domain of natural endowments,only agricultural capital emerged as significant.This is a result that corresponds to expectations,given that foods and beverages are the primary source of demand in the tourism economy.Hence,investments in agricultural technology may foment linkages with the tourism market.It is also worth mentioning that for significant backward linkages to emerge with local agriculture,a larger scale of tourism may be important. According to the regression results,a strong tourism–agriculture nexus will not necessarily develop at a small scale of tourism demand. It appears that variables related to the entrepreneurial capital of the host economy are of notable explanatory significance.The human development index(HDI), which is used to measure a country's general level of development,is significantly and positively associated with tourism linkages.One plausible explanation for this is that international tourists,who often originate in high-income countries,may feel more comfortable and thus be inclined to consume more in a host country that has a life-style to which they can relate easily.Moreover,it is important to remember that the HDI also captures the relative achievements of countries in the level of health and education of the population.Therefore,a higher HDI reflects a healthier and more educated workforce,and thus,the quality of local entrepreneurship.Related to this point,it is important to underscore that the level of participation of women in the host economy also has a significantly positive effect on linkages.In sum, enhancing local entrepreneurial capital may expand the linkages between tourism and other sectors of the host country.

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