当前位置:
搜档网 › 基于verilog音乐播放代码
基于verilog音乐播放代码
module song(clk,beep,out);
input clk;
output beep,out;
reg beep_r;
reg[7:0] state;
reg[15:0] count,count_end;
reg[23:0] count1;
assign out=beep;
parameter L_5=16'd63775,
L_6=16'd56818,
M_1=16'd47773,
M_2=16'd42567,
M_3=16'd37919,
M_5=16'd31887,
M_6=16'd28409,
H_1=16'd23923;
parameter TIME=12000000;
assign beep=beep_r;
always@(posedge clk)
begin
count<=count+1'b1;
if(count==count_end)
begin
count<=16'h0;
beep_r<=!beep_r;
end
end
always@(posedge clk)
begin
if(count1
count_end=H_1;
8'd113,8'd114,8'd115,8'd116: count_end=M_5;
8'd117,8'd118,8'd119: count_end=M_3;
8'd120,8'd121: count_end=M_6;
8'd122,8'd123,8'd124,8'd125: count_end=M_2;
8'd126: count_end=M_1;
8'd127,8'd128: count_end=M_2;
8'd129,8'd130: count_end=M_3;
8'd131,8'd132,8'd133,8'd134: count_end=M_1;
8'd135,8'd136,8'd137: count_end=L_6;
8'd138,8'd139: count_end=M_5;
8'd140,8'd141,8'd142,8'd143: count_end=M_1;
8'd144,8'd145,8'd146,8'd147: count_end=M_1;
default:count_end=16'hffff;
endcase
end
end
endmodule