高频4A的同步整流驱动芯片TPS28226

FEATURES

DESCRIPTION

APPLICATIONS TPS28226

SLUS791–OCTOBER 2007

https://www.sodocs.net/doc/2d13205990.html, High-Frequency 4-A Sink Synchronous MOSFET Drivers

?Drives Two N-Channel MOSFETs with 14-ns

Adaptive Dead Time

The TPS28226is a high-speed driver for N-channel complimentary driven power MOSFETs with adaptive ?Gate Drive Voltage:6.8V Up to 8.8V

dead-time control.This driver is optimized for use in ?Wide Power System Train Input Voltage:3V

variety of high-current one and multi-phase dc-to-dc Up to 27V

converters.The TPS28226is a solution that provides ?Wide Input PWM Signals:2.0V up to 13.2-V

highly efficient,small size low EMI emmissions.Amplitude

The performance is achieved by up to 8.8-V gate ?Capable Drive MOSFETs with ≥40-A Current

drive voltage,14-ns adaptive dead-time control,14-ns per Phase

propagation delays and high-current 2-A source and 4-A sink drive capability.The 0.4-?impedance for ?High Frequency Operation:14-ns Propagation

the lower gate driver holds the gate of power Delay and 10-ns Rise/Fall Time Allow F SW -2

MOSFET below its threshold and ensures no MHz

shoot-through current at high dV/dt phase node ?Capable Propagate <30-ns Input PWM Pulses

transitions.The bootstrap capacitor charged by an ?Low-Side Driver Sink On-Resistance (0.4?)

internal diode allows use of N-channel MOSFETs in Prevents dV/dT Related Shoot-Through

half-bridge configuration.Current

The TPS28226features a 3-state PWM input ?3-State PWM Input for Power Stage Shutdown

compatible with all multi-phase controllers employing 3-state output feature.As long as the input stays ?Space Saving Enable (input)and Power Good

within 3-state window for the 250-ns hold-off time,the (output)Signals on Same Pin

driver switches both outputs low.This shutdown ?Thermal Shutdown

mode prevents a load from the reversed-?UVLO Protection

output-voltage.?Internal Bootstrap Diode

The other features include under voltage lockout,?Economical SOIC-8and Thermally Enhanced

thermal shutdown and two-way enable/power good 3-mm x 3-mm DFN-8Packages

signal.Systems without 3-state featured controllers can use enable/power good input/output to hold both ?High Performance Replacement for Popular

outputs low during shutting down.

3-State Input Drivers The TPS28226is offered in an economical SOIC-8

and thermally enhanced low-size Dual Flat No-Lead

(DFN-8)packages.The driver is specified in the

?Multi-Phase DC-to-DC Converters with Analog extended temperature range of –40°C to 125°C with

or Digital Control the absolute maximum junction temperature 150°C.?

Desktop and Server VRMs and EVRDs ?

Portable/Notebook Regulators ?Synchronous Rectification for Isolated Power Supplies

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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FUNCTIONAL BLOCK DIAGRAM

VDD EN /PG BOOT

UGATE PHASE LGATE

GND

PWM

TYPICAL APPLICATIONS

TPS28226

SLUS791–OCTOBER 2007One-Phase POL Regulator

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TPS28226

SLUS791–OCTOBER 2007

TYPICAL APPLICATIONS (continued)

Driver for Synchronous Rectification with Complementary Driven MOSFETs

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TPS28226

SLUS791–OCTOBER 2007TYPICAL APPLICATIONS (continued)

Multi-Phase Synchronous Buck Converter

ORDERING INFORMATION (1)(2)(3)

PART NUMBER TEMPERATURE RANGE,T A =T J PACKAGE

TAPE AND REEL QTY.TPS28226Plastic 8-pin SOIC (D)

75per tube TPS28226D Plastic 8-pin SOIC (D)

2500TPS28226DR -40C to 125C Plastic 8-pin DFN (DRB)

250TPS28226DRBT Plastic 8-pin DFN (DRB)

3000TPS28226DRBR (1)

SOIC-8(D)and DFN-8(DRB)packages are available taped and reeled.Add T suffix to device type (e.g.TPS28226DRBT)to order taped devices and suffix R (e.g.TPS28226DRBR)to device type to order reeled devices.(2)

The SOIC-8(D)and DFN-8(DRB)package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1at 255C to 260C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.(3)In the DFN package,the pad underneath the center of the device is a thermal substrate.The PCB “thermal land”design for this

exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s).This combination of

vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential.This pad should

be either grounded for best noise immunity,and it should not be connected to other nodes.

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ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS(1) RECOMMENDED OPERATING CONDITIONS

TPS28226 SLUS791–OCTOBER2007

over operating free-air temperature range(unless otherwise noted)(1)(2)

TPS28226VALUE UNIT

Input supply voltage range,V DD(3)–0.3to8.8

Boot voltage,V BOOT–0.3to33

DC–2to32or V BOOT+0.3–V DD whichever is less

Phase voltage,V PHASE

Pulse<400ns,E=20μJ–7to33.1or V BOOT+0.3–V DD whichever is less

Input voltage range,V PWM,V EN/PG–0.3to13.2

V PHASE–0.3to V BOOT+0.3,(V BOOT–V PHASE<8.8)V Output voltage range,V UGATE

Pulse<100ns,E=2μJ V PHASE–2to V BOOT+0.3,(V BOOT–V PHASE<8.8)

–0.3to V DD+0.3

Output voltage range,V LGATE

Pulse<100ns,E=2μJ–2to V DD+0.3

ESD rating,HBM2k

ESD rating,HBM ESD rating,CDM500 Continuous total power dissipation See Dissipation Rating Table

Operating virtual junction temperature range,T J–40to150

Operating ambient temperature range,T A–40to125

°C Storage temperature,T stg–65to150

Lead temperature(soldering,10sec.)300

(1)Stresses beyond those listed under“absolute maximum ratings”may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under“recommended operating conditions”is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)These devices are sensitive to electrostatic discharge;follow proper device handling procedures.

(3)All voltages are with respect to GND unless otherwise noted.Currents are positive into,negative out of the specified terminal.Consult

Packaging Section of the Data book for thermal limitations and considerations of packages.

DERATING FACTOR T A<25°C T A=70°C T A=85°C BOARD PACKAGE RθJC RθJA

ABOVE T A=25°C POWER RATING POWER RATING POWER RATING High-K(2)D39.4°C/W100C/W10mW/C 1.25W0.8W0.65W High-K(3)DRB 1.4°C/W48.5C/W20.6mW/C 2.58W 1.65W 1.34W

(1)These thermal data are taken at standard JEDEC test conditions and are useful for the thermal performance comparison of different

packages.The cooling condition and thermal impedance RθJA of practical design is specific.

(2)The JEDEC test board JESD51-7,3-inch x3-inch,4-layer with1-oz internal power and ground planes and2-oz top and bottom trace

layers.

(3)The JEDEC test board JESD51-5with direct thermal pad attach,3-inch x3-inch,4-layer with1-oz internal power and ground planes and

2-oz top and bottom trace layers.

over operating free-air temperature range(unless otherwise noted)

MIN TYP MAX UNIT

V DD Input supply voltage 6.87.28

V

V IN Power input voltage332V–VDD

T J Operating junction temperature range–40125C

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ELECTRICAL CHARACTERISTICS (1)TPS28226SLUS791–OCTOBER 2007V DD =7.2V,EN/PG pulled up to V DD by 100-k ?resistor,T A =T J =–40°C to 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT UNDER VOLTAGE LOCKOUT

Rising threshold

6.35 6.70Falling threshold

V PWM =0V 4.7 5.0V Hysteresis

1.00 1.35BIAS CURRENTS

I DD(off)

Bias supply current V EN/PG =low,PWM pin floating 350μA I DD Bias supply current V EN/PG =high,PWM pin floating

500INPUT (PWM)V PWM =5V

185I PWM Input current μA V PWM =0V

–200PWM 3-state rising threshold (2) 1.0V PWM 3-state falling threshold V PWM PEAK =5V

3.4 3.8

4.0t HLD_R 3-state shutdown Hold-off time 250ns T MIN PWM minimum pulse to force U GATE pulse C L =3nF at U GATE ,V PWM =5V

30ENABLE/POWER GOOD (EN/PG)Enable high rising threshold PG FET OFF

1.7

2.1Enable low falling threshold PG FET OFF

0.8 1.0V Hysteresis 0.350.70

Power good output V DD =2.5V

0.2UPPER GATE DRIVER OUTPUT (UGATE)Source resistance 500mA source current

1.0

2.0ΩSource current (2)V UGATE-PHASE =2.5V

2.0A t RU Rise time C L =3nF

10ns Sink resistance 500mA sink current

1.0

2.0ΩSink current (2)V UGATE-PHASE =2.5V

2.0A t FU

Fall time C L =3nF 10ns (1)

Typical values for T A =25C

(2)Not tested in production

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TPS28226 SLUS791–OCTOBER2007

ELECTRICAL CHARACTERISTICS(continued)

V DD=7.2V,EN/PG pulled up to V DD by100-k?resistor,T A=T J=–40°C to125°C(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LOWER GATE DRIVER OUTPUT(LGATE)

Source resistance500mA source current 1.0 2.0Ω

Source current(3)V LGATE=2.5V 2.0A

t RL Rise time(3)C L=3nF10ns

Sink resistance500mA sink current0.4 1.0Ω

Sink current(3)V LGATE=2.5V 4.0A

Fall time(3)C L=3nF5ns

SWITCHING TIME

t DLU UGATE turn-off propagation Delay C L=3nF14

t DLL LGATE turn-off propagation Delay C L=3nF14

ns t DTU Dead time LGATE turn-off to UGATE turn-on C L=3nF14

t DTL Dead time UGATE turn-off to LGATE turn-on C L=3nF14

BOOTSTRAP DIODE

V F Forward voltage Forward bias current100mA 1.0V

THERMAL SHUTDOWN

Rising threshold(3)150160170

Falling threshold(3)130140150°C

Hysteresis20

(3)Not tested in production

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DEVICE INFORMATION

UGATE BOOT PWM GND PHASE

EN/PG

VDD

LGATE

BOOT

PWM

VDD EN/PG LG AT E

GND U G AT E

PHASE

VDD EN /PG BOOT UGATE PHASE

LGATE GND

PWM

TPS28226

SLUS791–OCTOBER 2007FUNCTIONAL BLOCK DIAGRAM

A.For the TPS28226DRB device the thermal PAD on the bottom side of package must be soldered and connected to

the GND pin and to the GND plane of the PCB in the shortest possible way.See Recommended Land Pattern in the

Application section.

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TRUTH TABLE

TPS28226 SLUS791–OCTOBER2007

TERMINAL FUNCTIONS

TERMINAL

I/O DESCRIPTION

SOIC-8DRB-8NAME

11UGATE O Upper gate drive sink/source output.Connect to gate of high-side power N-Channel MOSFET.

Floating bootstrap supply pin for the upper gate drive.Connect the bootstrap capacitor between 22BOOT I/O this pin and the PHASE pin.The bootstrap capacitor provides the charge to turn on the upper

MOSFET.

The PWM signal is the control input for the driver.The PWM signal can enter three distinct states 33PWM I during operation,see the3-state PWM Input section under DETAILED DESCRIPTION for further

details.Connect this pin to the PWM output of the controller.

44GND—Ground pin.All signals are referenced to this node.

Exposed Thermal

—Connect directly to the GND for better thermal performance and EMI

die pad pad

Lower gate drive sink/source output.Connect to the gate of the low-side power N-Channel 55LGATE O

MOSFET.

66VDD I Connect this pin to a5-V bias supply.Place a high quality bypass capacitor from this pin to GND.

Enable/Power Good input/output pin with1MΩimpedance.Connect this pin to HIGH to enable and

LOW to disable the device.When disabled,the device draws less than350μA bias current.If the 77EN/PG I/O

V DD is below UVLO threshold or over temperature shutdown occurs,this pin is internally pulled

low.

Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET.This pin 88PHASE I

provides a return path for the upper gate driver.

V DD FALLING>3V AND T J<150°C

V DD RISING<3.5V EN/PG FALLING>1.0V PIN EN/PG RISING

OR T J>160°C PWM>1.5V AND PWM SIGNAL SOURCE IMPEDANCE

<1.7V PWM<1V

T RISE/T FALL<200ns>40k?FOR>250ns(3-State)(1) LGATE Low Low High Low Low

UGATE Low Low Low High Low

EN/PG Low

(1)During power up,the TPS28226is in3-state and both UGATE and LGATE outputs are kept low.To exit the3-state condition,the PWM

signal should go high followed by one low PWM signal.The first high PWM pulse is ignored by the driver and keeps UGATE output low, but the following low PWM signal drives LGATE high.

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PWM UGATE

goes High and then Low TPS28226

SLUS791–OCTOBER 2007TPS28226TIMING DIAGRAM

https://www.sodocs.net/doc/2d13205990.html, TYPICAL CHARACTERISTICS

?40125300

340380420460

500

25

320360400440480

T J ? Temperature ? °C I D D (o f f ) ? B i a s S u p p l y ? μ

A 2.003.50

4.506.002.50

3.00

4.00

5.005.50U V L O ? U n d e r V o l t a g e L o c k o u t ? V ?40125TJ ? Temperature ? C

256.508.007.007.50

0.0P W M ? P W M 3?S t a t e T h r e s h o l d ? V ?40125

252.03.05.00.5

1.0

2.52.54.51.54.0

T J ? Temperature ? °C ?4012525

0.00

0.751.252.00

0.250.501.001.501.75

T J ? Temperature ? °C

E N /P G ? E n a b l e /P o w e r G o o d ? V TPS28226SLUS791–OCTOBER 2007

BIAS SUPPLY CURRENT vs UNDER VOLTAGE LOCKOUT THRESHOLD TEMPERATURE vs (V EN/PG =Low,PWM Input Floating,V DD =7.2V)

TEMPERATURE Figure 1.

Figure 2.ENABLE/POWER GOOD THRESHOLD PWM 3-STATE THRESHOLDS,(5-V Input Pulses)vs vs TEMPERATURE (V DD =7.2V)TEMPERATURE,(V =7.2V)

Figure 3.Figure 4.

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?4012525

0.75

1.25

2.00

0.25

0.50

1.001.501.75

T J ? Temperature ? °C R O U T ? O u t p u t I m p e d a n c e ? ?

0?40125250.751.252.000.250.501.001.50

1.75T J ? Temperature ? °C R O U T ? O u t p u t I m p e d a n c e ? ??4012525

461012145791113

8T J ? Temperature ? °C t R L /t F L ? R i s e a n d F a l l T i m e ? n s

6

8

111315

7

9101214

?40125

25T J ? Temperature ? °C

t R U /t F U ? R i s e a n d F a l l T i m e ? n s TPS28226SLUS791–OCTOBER 2007TYPICAL CHARACTERISTICS (continued)

UGATE DC OUTPUT IMPEDANCE LGATE DC OUTPUT IMPEDANCE vs vs TEMPERATURE,(V DD =7.2V)

TEMPERATURE (V DD =7.2V)

Figure 5.

Figure 6.UGATE RISE AND FALL TIME LGATE RISE AND FALL TIME vs vs TEMPERATURE (V DD =7.2V,C LOAD =3nF)

TEMPERATURE (V DD =7.2V,C LOAD =3nF)Figure 7.Figure 8.

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2025

3051015?4012525

T J ? Temperature ? °C

t D L U /t D L L ? U G A T E a n d L G A T E ? n s ?40125250.012.517.520.0

2.5

7.510.05.0

15.0

T J ? Temperature ? °C t D T U /t D T L ? U G A T E a n d L G A T E ? n s 0.5

0.81.01.3

0.6

0.70.91.11.2

?40125

25T J ? Temperature ? °C

V F ? F o r w a r d V o l t a g e ? V 0525

30101520?40125

25

T J ? Temperature ? °C T M I N ? M i n i m u m S h o r t P u l s e ? n s TPS28226SLUS791–OCTOBER 2007

TYPICAL CHARACTERISTICS (continued)

UGATE AND LGATE (Turning OFF Propagation Delays)UGATE AND LGATE (Dead Time)vs vs TEMPERTURE (V DD =7.2V,C LOAD =3nF)

TEMPERTURE (V DD =7.2V,C LOAD =3nF)

Figure 9.Figure 10.

UGATE MINIMUM SHORT PULSE BOOTSTRAP DIODE FORWARD VOLTAGE vs vs TEMPERATURE (V DD =7.2V,C LOAD =3nF)

TEMPERATURE (V DD =7.2V,I F =100mA)Figure 11.

Figure 12.

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0200

10001200

40060080010030050070015001700900110019001300

F SW ? Switching Frequency ? kHz P D I S S ? D i s s i p a t e d P o w e r ? m W 0

155

101003005007001500170090011001900

1300F SW ? Switching Frequency ? kHz

I D D ? B i a s S u p p l y C u r r e n t ? m A PWM UGATE LGATE V DD = 7.2 V, C L = 3 nF , T J = 25°C t ? Time ? 10 ns/div.

V o l t a g e ? 5 V /d i v .PWM UGATE

LGATE

V DD = 7.2 V, C L = 3 nF , T J = 25°C

t ? Time ? 10 ns/div.V o l t a g e ? 5 V /d i v .TPS28226SLUS791–OCTOBER 2007TYPICAL CHARACTERISTICS (continued)

BIAS SUPPLY CURRENT DRIVER DISSIPATED POWER vs vs SWITCHING FREQUENCY SWITCHING FREQUENCY (V DD =7.2V,No Load,T J =25°C)

(Different Load Charge,V DD =7.2V,T J =25°C)

Figure 13.Figure 14.

PWM INPUT RISING SWITCHING WAVEFORMS PWM INPUT FALLING SWITCHING WAVEFORMS

Figure 15.Figure 16.

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UGATE LGATE V DD = 7.2 V, C L = 3 nF , T J = 25°C t ? Time ? 20 ns/div.

V o l t a g e ? 5 V /d i v .PWM ? 2 V/div.3?St Trigger, High = 3?St UGATE ? 10 V/div.LGATE ? 10 V/div.

V o l t a g e t ? Time ? 5 μs/div.TPS28226SLUS791–OCTOBER 2007

TYPICAL CHARACTERISTICS (continued)

NORMAL AND 3-STATE OPERATION MINIMUM UGATE PULSE SWITCHING WAVEFORMS ENTER/EXIT CONDITIONS

Figure 17.Figure 18.The 3-state upper threshold reverts to the 2-V level after the TPS28226had been in 3-state for about 2.5μs.

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DETAILED DESCRIPTION

Under Voltage Lockout (UVLO)

Output Active Low TPS28226SLUS791–OCTOBER 2007The TPS28226incorporates an under voltage lockout circuit that keeps the driver disabled and external power

FETs in an OFF state when the input supply voltage V DD is insufficient to drive external power FETs reliably.

During power up,both gate drive outputs remain low until voltage V DD reaches UVLO threshold,typically 6.35V

for the TPS28226.Once the UVLO threshold is reached,the condition of gate drive outputs is defined by the

input PWM and EN/PG signals.During power down the UVLO threshold is set lower,typically 5.0V for the

TPS28226.The 1.35V for the TPS28226hysteresis is selected to prevent the driver from turning ON and OFF

while the input voltage crosses UVLO thresholds,especially with low slew rate.The TPS28226has the ability to

send a signal back to the system controller that the input supply voltage V DD is insufficient by internally pulling

down the EN/PG pin.The TPS28226releases EN/PG pin immediately after the V DD has risen above the UVLO

threshold.

The output active low circuit effectively keeps the gate outputs low even if the driver is not powered up.This

prevents open gate conditions on the external power FETs and accidental turn ON when the main power stage

supply voltage is applied before the driver is powered up.For the simplicity,the output active low circuit is shown

in a block diagram as the resistor connected between LGATE and GND pins with another one connected

between UGATE and PHASE pins.

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V DD = 6.8 V to 8.0 V for the TPS28226

TPS28226SLUS791–OCTOBER 2007The Enable/Power Good circuit allows the TPS28226to follow the PWM input signal when the voltage at EN/PG

pin is above 2.1V maximum.This circuit has a unique two-way communication capability.This is illustrated by

Figure 19.

Figure 19.Enable/Power Good Circuit

The EN/PG pin has approximately 1-k ?internal series resistor.Pulling EN/PG high by an external ≥20-k ?

resistor allows two-way communication between controller and driver.If the input voltage V DD is below UVLO

threshold or thermal shut down occurs,the internal MOSFET pulls EN/PG pin to GND through 1-k ?resistor.The

voltage across the EN/PG pin is now defined by the resistor divider comprised by the external pull up resistor,

1-k ?internal resistor and the internal FET having 1-k ?R DS(on).Even if the system controller allows the driver to

start by setting its own enable output transistor OFF,the driver keeps the voltage at EN/PG low.Low EN/PG

signal indicates that the driver is not ready yet because the supply voltage V DD is low or that the driver is in

thermal shutdown mode.The system controller can arrange the delay of PWM input signals coming to the driver

until the driver releases EN/PG pin.If the input voltage V DD is back to normal,or the driver is cooled down below

its lower thermal shutdown threshold,then the internal MOSFET releases the EN/PG pin and normal operation

resumes under the external Enable signal applied to EN/PG input.Another feature includes an internal 1-M ?

resistor that pulls EN/PG pin low and disables the driver in case the system controller accidentally loses

connection with the driver.This could happen if,for example,the system controller is located on a separate PCB

daughter board.

The EN/PG pin can serve as the second pulse input of the driver additionally to PWM input.The delay between

EN/PG and the UGATE going high,provided that PWM input is also high,is only about 30ns.If the PWM input

pulses are synchronized with EN/PG input,then when PWM and EN/PG are high,the UGATE is high and

LGATE is low.If both PWM and EN/PG are low,then UGATE and LGATE are both low as well.This means the

driver allows operation of a synchronous buck regulator as a convertional buck regulator using the body diode of

the low side power MOSFET as the freewheeling diode.This feature can be useful in some specific applications

to allow startup with a pre-biased output or,to improve the efficiency of buck regulator when in power saving

mode with low output current.

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3-State

Input TPS28226SLUS791–OCTOBER 2007As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below).The dead-time

control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot

through current through the external power FETs.Additionally to operate under periodical pulse sequencing,the

TPS28226has a self-adjustable PWM 3-state input circuit.The 3-state circuit sets both gate drive outputs low,

and thus turns the external power FETs OFF if the input signal is in a high impedance state for at least 250ns

typical.At this condition,the PWM input voltage level is defined by the internal 27k ?to 13k ?resistor divider

shown in the block diagram.This resistor divider forces the input voltage to move into the 3-state window.Initially

the 3-state window is set between 1.0-V and 2.0-V thresholds.The lower threshold of the 3-state window is

always fixed at about 1.0V.The higher threshold is adjusted to about 75%of the input signal amplitude.The

3-state upper threshold reverts to the 2-V level after the TPS28226had been in 3-state for about 2.5μs.The

self-adjustable upper threshold allows shorter delay if the input signal enters the 3-state window while the input

signal was high,thus keeping the high-side power FET in ON state just slightly longer than 250ns time constant

set by an internal 3-state timer.Both modes of operation,PWM input pulse sequencing and the 3-state condition,

are illustrated in the timing diagrams shown in Figure 18.The self-adjustable upper threshold allows operation in

wide range amplitude of input PWM pulse waveforms in Figure 20and Figure 21illustrates the

TPS28226operation at normal and 3-state mode with the input pulse V After

entering into the 3-state window and staying within the window for the hold-off time,the PWM input signal level is

defined by the internal resistor divider and,depending on the input pulse amplitude,can be pulled up above the

normal PWM pulse amplitude (Figure 21)or down below the normal input PWM pulse (Figure 20).

TPS282263-State Exit Mode:

?To exit the 3-state operation mode,the PWM signal should go high and then low at least once.

This is necessary to restore the voltage across the bootstrap capacitor that could be discharged during the

3-state mode if the 3-state condition lasts long enough.

Figure 20.6-V Amplitude PWM Pulse Figure 21.2.5-V Amplitude PWM Pulse

NOTE:

The driver sets UGATE low and LGATE high when PWM is low.When the PWM goes

high,UGATE goes high and LGATE goes low.

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TPS28226 SLUS791–OCTOBER2007

IMPORTANT NOTE:Any external resistor between PWM input and GND with the value lower than40k?can interfere with the3-state thresholds.If the driver is intended to operate in the3-state mode,any resistor below 40k?at the PWM and GND should be avoided.A resistor lower than3.5k?connected between the PWM and GND completely disables the3-state function.In such case,the3-state window shrinks to zero and the lower 3-state threshold becomes the boundary between the UGATE staying low and LGATE being high and vice versa depending on the PWM input signal applied.It is not necessary to use a resistor<3.5k?to avoid the3-state condition while using a controller that is3-state capable.If the rise and fall time of the input PWM signal is shorter than250ns,then the driver never enter into the3-state mode.

In the case where the low-side MOSFET of a buck converter stays on during shutdown,the3-state feature can be fused to avoid negative resonent voltage across the output capacitor.This feature also can be used during start up with a pre-biased output in the case where pulling the output low during the startup is not allowed due to system requirements.If the system controller does not have the3-state feature and never goes into the high-impedance state,then setting the EN/PG signal low will keep both gate drive outputs low and turn both low-and high-side MOSFETs OFF during the shut down and start up with the pre-biased output.

The self-adjustable input circuit accepts wide range of input pulse amplitudes(2V up to13.2V)allowing use of a variety of controllers with different outputs including logic level.The wide PWM input voltage allows some flexibility if the driver is used in secondary side synchronous rectifier circuit.The operation of the TPS28226with a12-V input PWM pulse amplitude,and with V DD=7.2V shown in Figure22.

Figure22.12-V PWM Pulse at V DD=7.2V

https://www.sodocs.net/doc/2d13205990.html,

Bootstrap Diode

Upper And Lower Gate Drivers

Dead-Time Control

Thermal Shutdown TPS28226SLUS791–OCTOBER 2007The bootstrap diode provides the supply voltage for the UGATE driver by charging the bootstrap capacitor

connected between BOOT and PHASE pins from the input voltage VDD when the low-side FET is in ON state.

At the very initial stage when both power FETs are OFF,the bootstrap capacitor is pre-charged through this path

including the PHASE pin,output inductor and large output capacitor down to GND.The forward voltage drop

across the diode is only 1.0V at bias current 100mA.This allows quick charge restore of the bootstrap capacitor

during the high-frequency operation.

The upper and lower gate drivers charge and discharge the input capacitance of the power MOSFETs to allow

operation at switching frequencies up to 2MHz.The output stage consists of a P-channel MOSFET providing

source output current and an N-channel MOSFET providing sink current through the output stage.The ON state

resistances of these MOSFETs are optimized for the synchronous buck converter configuration working with low

duty cycle at the nominal steady state condition.The UGATE output driver is capable of propagating PWM input

puses of less than 30-ns while still maintaining proper dead time to avoid any shoot through current conditions.

The waveforms related to the narrow input PWM pulse operation are shown in Figure 17.

The dead-time control circuit is critical for highest efficiency and no shoot through current operation througout the

whole duty cycle range with the different power MOSFETs.By sensing the output of driver going low,this circuit

does not allow the gate drive output of another driver to go high until the first driver output falls below the

specified threshold.This approach to control the dead time is called adaptive.The overall dead time also

includes the fixed portion to ensure that overlapping never exists.The typical dead time is around 14ns,

although it varies over the driver internal tolerances,layout and external MOSFET parasitic inductances.The

proper dead time is maintained whenever the current through the output inductor of the power stage flows in the

forward or reverse direction.Reverse current could happen in a buck configuration during the transients or while

dynamically changing the output voltage on the fly,as some microprocessors require.Because the dead time

does not depend on inductor current direction,this driver can be used both in buck and boost regulators or in any

bridge configuration where the power MOSFETs are switching in a complementary manner.Keeping the dead

time at short optimal level boosts efficiency by 1%to 2%depending on the switching frequency.Measured

switching waveforms in one of the practical designs show 10-ns dead time for the rising edge of PHASE node

and 22ns for the falling edge (Figure 28and Figure 29in the Application Section of the data sheet).

Large non-optimal dead time can cause duty cycle modulation of the dc-to-dc converter during the operation

point where the output inductor current changes its direction right before the turn ON of the high-side MOSFET.

This modulation can interfere with the controller operation and it impacts the power stage frequency response

transfer function.As the result,some output ripple increase can be observed.The TPS28226driver is designed

with the short adaptive dead time having fixed delay portion that eliminates risk of the effective duty cycle

modulation at the described boundary condition.

If the junction temperature exceeds 160°C,the thermal shutdown circuit will pull both gate driver outputs low and

thus turning both,low-side and high-side power FETs OFF.When the driver cools down below 140°C after a

thermal shutdown,then it resumes its normal operation and follows the PWM input and EN/PG signals from the

external control circuit.While in thermal shutdown state,the internal MOSFET pulls the EN/PG pin low,thus

setting a flag indicating the driver is not ready to continue normal operation.Normally the driver is located close

to the MOSFETs,and this is usually the hottest spots on the PCB.Thus,the thermal shutdown feature of

TPS28226can be used as an additional protection for the whole system from overheating.

同步整流技术分享

江苏宏微科技股份有限公司 Power for the Better
同步整流技术及主要拓扑电路
宏微科技市场部
2015-9-16

Contents
? 同步整流电路概述 ? 典型电路及其特点 ? 损耗分析 ? 同步整流电路中常见问题 ? MOSFET选型设计参考
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? 同步整流技术概述 ? 典型电路及其特点 ? 损耗分析 ? 同步整流电路中常见问题 ? MOSFET选型设计参考
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同步整流技术概述
由于中低压MOSFET具有很小的导通电阻，在有电流通过时产生的电压降很 小，可以替代二极管作为整流器件，可以提高变换器的效率。
diode
MOSFET
MOSFET作整流器时，栅源极间电压必须与被整流电压的相位保持同步关系才 能完成整流功能，故称同步整流技术。 MOSFET是电压控制型开关器件，且没有反向阻断能力，必须在其栅-源之 间加上驱动电压来控制器漏-源极之间的导通和关断。这是同步整流设计的难 点和重点。 根据其控制方式，同步整流的驱动电路分为 ?自驱动方式； ? 独立控制电路他驱方式； ? 部分自驱+部分他驱方式结合；
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同步整流电路

随着现代电子技术向高速度高频率发展的趋势，电源模块的发展趋势必然是朝着更低电压、更大电流的方向发展，电源整流器的开关损耗及导通压降损耗也就成为电源功率损耗的重要因素。而在传统的次级整流电路中，肖特基二极管是低电压、大电流应用的首选。其导通压降基本上都大于0.4V，当电源模块的输出电压随着现代电子技术发展继续降低时，电源模块的效率就低得惊人了，例如在输出电压为3.3V时效率降为80%，1.5V输出时效率不到70%，这时再采用肖特基二极管整流方式就变得不太可能了。 为了提高效率降低损耗，采用同步整流技术已成为低电压、大电流电源模块的一种必然手段。同步整流技术大体上可以分为自驱动（selfdriven）和他驱动（controldriven）两种方式。本文介绍了一种具有预测时间和超低导通电阻（低至2.8mΩ/25℃）的他驱动同步整流技术，既达到了同步整流的目的，降低了开关损耗和导通损耗，又解决了交叉导通问题，使同步整流的效率高达95%，从而使整个电源的效率也高达90%以上。 1SRM4010同步整流模块功能简介 SRM4010是一种高效率他激式同步整流模块，它直接和变压器的次级相连，可提供40A的输出电流，输出电压范围在1∽5V之间。它能够在200∽400kHz 工作频率范围内调整，且整流效率高达95%。如果需要更大的电流，还可以直接并联使用，使设计变得非常简单。 SRM4010模块是一种9脚表面封装器件，模块被封装在一个高强电流接口装置包里，感应系数极低，接线端功能强大，具有大电流低噪声等优异特性。 SRM4010引脚功能及应用方式一览表 引脚号引脚名称引脚功能应用方式 1CTCHCatch功率MOSFET漏极接滤波电感和变压器次级正端 2FWDForward功率MOSFET漏极接变压器次级负端 3SGND外控信号参考地外围控制电路公共地 4REGin内部线性调整器输入可以外接辅助绕组或悬空 5REGout5V基准输出可为次级反馈控制电路提供电压 6PGND同步整流MOSFET功率地Catch和Forward功率MOSFET公共地 7CDLY轻载复位电容端设置变压器轻载时的复位时间 8CPDT同步整流预测时间电容端Catch同步整流管设置预置时间

半桥同步整流设计报告

\ 半桥倍流同步整流电源的设计 摘要：现如今，微处理器要求更低的供电电压，以降低功耗，这就要求供电系 统能提供更大的输出电流，低压大电流技术越发引起人们的广泛关注。本电源系统以对称半桥为主要拓扑，结合倍流整流和同步整流的结构，并且使用MSP430单片机控制和采样显示，实现了5V，15A大电流的供电系统。效率较高，输出纹波小。 关键词：对称半桥，倍流整流，同步整流，SG3525 一、方案论证与比较 1 电源变换拓扑方案论证 方案一：（如下图）此电路为传统的半桥拓扑。由于MOS管只承受一倍电源电压，而不像单端类的承受两倍电源电压，且较之全桥拓扑少了两个昂贵的MOS 管，因此得到很大的应用。但在低压大电流的设计中，输出整流管的损耗无疑会大大降低效率，而且电感的设计也会变得困难，因此不适合大电流的设计。 方案二：传统半桥+同步整流。将上图半桥的输出整流管改为低导通内阻的MOSFET。如此可大大减小输出整流的损耗，提高效率。比较适合大电流的整流方案，但变压器的绕制和电感的设计较麻烦。 方案三：（如下图）半桥倍流同步整流。倍流整流很早就被人提出，它的特点是变压器输出没有中心抽头，这就大大简化了变压器的设计，并且提高了变压器的利用率。而流过变压器和输出电感的电流仅有输出电流的一半，这使得变压器和电感的制作变得简单。并且由波形分析可以知道，输出电流的纹波是互相抵消的。该电路的不足是电路时序有要求，控制稍显复杂。由上分析我们选择方案三。 2 控制方案选择 方案一：由于控制芯片SG3525输出两路互补对称的PWM信号，则可将控制信号做如下设置（如下图）。 将驱动Q1的信号与Q4同步起来，Q2和Q3的信号同步，则可以实现倍流同步整流的时序同步，方案简单易行，但由于SG3525在输出较小占空比时有较大的死区，则输出MOSFET的续流二极管会产生较大的损耗。 方案二：。。。。。反激变换。。。。将SG3525的驱动信号反向后送入输出整流MOS 管，如此可以极大的减少低占空比时的损耗，且仅需一对反向驱动，故选用方案

同步整流技术总结

同步整流总结 1概述 近年来，为了适应微处理器的发展，模块电源的发展呈现两个明显的发展趋势：低 压和快速动态响应，在过去的10年中，模块电源大大改善了分布式供电系统的面貌。即使是在对成本敏感器件如线路卡，单板安装，模块电源也提供了诱人的解决方案。然而，高速处理器持续降低的工作电压需要一个全新的，适应未来的电压方案，尤其考虑到肖特级二极管整流模块不能令人满意的效率。同步整流电路正是为了适应低压输出要求应运而生的。由于一般的肖特基二极管的正向压降为0.3V以上，在低压输出时模块的效率 就不能做的很高，有资料表明采用肖特基二极管的隔离式DC-DC模块电源的效率可以 按照下式进行估算： V out V out (0.1 V out V cu V f) 0.1 V out—原边和控制电路损耗 V cu —印制板的线路损耗 V f —整流管导通压降损耗 我们假设采用0.4V的肖特基整流二极管，印制板的线路损耗为0.1V，则1.8V的模 块最大的估算效率为 72%。这意味着28%的能量被模块内部损耗了。其中由于二极管导通压降造成的损耗占了约15%。随着半导体工艺的发展，低压功率MOS管的的有着越 来越小的通态电阻，越来越低的开关损耗，现在IR公司最新的技术可以制作30V/2.5m Q的MOS管，在电流为15A时，导通压降为0.0375,比采用肖特基二极管低了一个数量级。所以近年来对同步整流电路的研究已经引起了人们的极大关注。在中大功率低压输出的DC-DC变换器的产品开发中，采用低压功率MOSFET替代肖特基二极管的方案 得到了广泛的认同。今天，采用同步整流技术的ON-BOARD 模块已经广泛应用于通讯 的所有领域。 2同步整流电路的工作原理 图1采用同步整流的正激电路示意图(无复位绕组)

同步整流技术最新

同步整流技术
电源网第20届技术交流会
邹超洋
2012.11

内 容 简 介
?同步整流简介。 ?同步整流的分类。 。 ?同步整流的驱动方式 ?同步整流的 MOSFET

同步整流简介
z 高速超大规模集成电路的尺寸的不断减小，功耗的不断降低，要求
供电电压也越来越低，而输出电流则越来越大。 z 电源本身的高输出电流、低成本、高频化（500kHz～1MHz）高 功率密度、高可靠性、高效率的方向发展。 z 在低电压、大电流输出DC-DC变换器的整流管，其功耗占变换器 全部功耗的50～60％。 z用低导通电阻MOSFET代替常规肖特基整流/续流二极管，可以大大 降低整流部分的功耗，提高变换器的性能，实现电源的高效率，高功 率密度。

同步整流简介
diode
=
MOSFET 代替diode
MOSFET
D
相当于二极管的功能 ?电流从S流向D ?V/I特性,工作于3rd 象限
G S
z 用MOSFET来代替二极管在电路中的整流功能
z 相对于二极管的开关算好极小 g 控制，可以根据系统的需要， z 整流的时序受到MOSFET的Vgs 把整流的损耗做到最小

同步整流简介
? 例如：一个5V?30A输出的电源
Diode
Vf=0.45V Ploss=0.45*30=13.5W Ploss/Po=13.5/45=30% /Po=13 5/45=30% Rdson=1.2m? Ploss=0.0012*30 0 0012*302=1.08W 1 08W Ploss/Po=1.08/45=2.4%
Mosfet
MBR8040(R)
SC010N04LS

同步整流电路分析

同步整流电路分析作者gyf2000 日期2007-4-22 20:21:00 一、传统二极管整流电路面临的问题 近年来，电子技术的发展，使得电路的工作电压越来越低、电流越来越大。低电压工作有利于降低电路的整体功率消耗，但也给电源设计提出了新的难题。 开关电源的损耗主要由3部分组成：功率开关管的损耗，高频变压器的损耗，输出端整流管的损耗。在低电压、大电流输出的情况下，整流二极管的导通压降较高，输出端整流管的损耗尤为突出。快恢复二极管（FRD）或超快恢复二极管（SRD）可达1.0～1.2V，即使采用低压降的肖特基二极管（SBD），也会产生大约0.6V的压降，这就导致整流损耗增大，电源效率降低。 举例说明，目前笔记本电脑普遍采用3.3V甚至1.8V或1.5V的供电电压，所消耗的电流可达20A。此时超快恢复二极管的整流损耗已接近甚至超过电源输出功率的50％。即使采用肖特基二极管，整流管上的损耗也会达到（18％～40％）P O，占电源总损耗的60％以上。因此，传统的二极管整流电路已无法满足实现低电压、大电流开关电源高效率及小体积的需要，成为制约DC／DC变换器提高效率的瓶颈。 二、同步整流的基本电路结构 同步整流是采用通态电阻极低的专用功率MOSFET，来取代整流二极管以降低整流损耗的一项新技术。它能大大提高DC／DC变换器的效率并且不存在由肖特基势垒电压而造成的死区电压。功率MOSFET属于电压控制型器件，它在导通时的伏安特性呈线性关系。用功率MOSFET做整流器时，要求栅极电压必须与被整流电压的相位保持同步才能完成整流功能，故称之为同步整流。 1、基本的变压器抽头方式双端自激、隔离式降压同步整流电路

同步整流电路分析

一、传统二极管整流电路面临的问题 近年来，电子技术的发展，使得电路的工作电压越来越低、电流越来越大。低电压工作有利于降低电路的整体功率消耗，但也给电源设计提出了新的难题。 开关电源的损耗主要由3部分组成：功率开关管的损耗，高频变压器的损耗，输出端整流管的损耗。在低电压、大电流输出的情况下，整流二极管的导通压降较高，输出端整流管的损耗尤为突出。快恢复二极管（FRD）或超快恢复二极管（SRD）可达～，即使采用低压降的肖特基二极管（SBD），也会产生大约的压降，这就导致整流损耗增大，电源效率降低。 举例说明，目前笔记本电脑普遍采用甚至或的供电电压，所消耗的电流可达20A。此时超快恢复二极管的整流损耗已接近甚至超过电源输出功率的50％。即使采用肖特基二极管，整流管上的损耗也会达到（18％～40％）P O，占电源总损耗的60％以上。因此，传统的二极管整流电路已无法满足实现低电压、大电流开关电源高效率及小体积的需要，成为制约DC ／DC变换器提高效率的瓶颈。 二、同步整流的基本电路结构 同步整流是采用通态电阻极低的专用功率MOSFET，来取代整流二极管以降低整流损耗的一项新技术。它能大大提高DC／DC变换器的效率并且不存在由肖特基势垒电压而造成的死区电压。功率MOSFET属于电压控制型器件，它在导通时的伏安特性呈线性关系。用功率MOSFET做整流器时，要求栅极电压必须与被整流电压的相位保持同步才能完成整流功能，故称之为同步整流。 1、基本的变压器抽头方式双端自激、隔离式降压同步整流电路 2、单端自激、隔离式降压同步整流电路 图1 单端降压式同步整流器的基本原理图 基本原理如图1所示，V1及V2为功率MOSFET，在次级电压的正半周，V1导通，V2关断，V1起整流作用；在次级电压的负半周，V1关断，V2导通，V2起到续流作用。同步整流电路的

100V 同步整流芯片ZCC6709C

快速关断智能型整流器概述 ZCC6709C是一个模拟低压降二极管集成电路，内置一个MOS开关管，取代在高效率反激电压转换器中的肖特基二极管。该芯片将外部同步整流器(SR) MOSFET 的正向压降控制在40mV左右，当电压为负时立即将其关闭。在低输出电压电池充电或高边整流的应用中ZCC6709C可以为自己产生供电电压。可编程的振铃检测电路，防止ZCC6709C在DCM和准谐振工作期间的错误开启。 特点 ●可低至0V的宽输出电压范围工作 ●无辅助线圈低输出整流下自供电工作。 ●逻辑电平SR MOSFETS方式工作。 ●符合能源之星1W待机的要求。 ●快速关闭和打开延迟时间。 ●静态电流。 ●支持DCM, Quasi-Resonant 和CCM 工作方式。 ●支持高边和底边整流。 ●典型笔记本适配器中电能节约达1.5W。 ●SOP8封装 应用 ● 工业电力系统。 ●分散电力系统。 ●电池电力系统。 ●反激式电源变换器。

快速关断智能型整流器典型应用 封装形式 极限值 VDD to VSS ........................................................................... –0.3V to +14V VD to Vss .................................................................. .... ..... –1V to + 80V HVC to VSS ................................................................... .... ..–1V to + 80V SLEW to VSS ..................................................................... –0.3V to +6.5V 连续功率损耗(TA = +25°C) 结温................................. ....... ........................ 150°C 引脚温度(焊接) ............................................... 260°C

高频4A的同步整流驱动芯片TPS28226

FEATURES DESCRIPTION APPLICATIONS TPS28226 SLUS791–OCTOBER 2007 https://www.sodocs.net/doc/2d13205990.html, High-Frequency 4-A Sink Synchronous MOSFET Drivers ?Drives Two N-Channel MOSFETs with 14-ns Adaptive Dead Time The TPS28226is a high-speed driver for N-channel complimentary driven power MOSFETs with adaptive ?Gate Drive Voltage:6.8V Up to 8.8V dead-time control.This driver is optimized for use in ?Wide Power System Train Input Voltage:3V variety of high-current one and multi-phase dc-to-dc Up to 27V converters.The TPS28226is a solution that provides ?Wide Input PWM Signals:2.0V up to 13.2-V highly efficient,small size low EMI emmissions.Amplitude The performance is achieved by up to 8.8-V gate ?Capable Drive MOSFETs with ≥40-A Current drive voltage,14-ns adaptive dead-time control,14-ns per Phase propagation delays and high-current 2-A source and 4-A sink drive capability.The 0.4-?impedance for ?High Frequency Operation:14-ns Propagation the lower gate driver holds the gate of power Delay and 10-ns Rise/Fall Time Allow F SW -2 MOSFET below its threshold and ensures no MHz shoot-through current at high dV/dt phase node ?Capable Propagate <30-ns Input PWM Pulses transitions.The bootstrap capacitor charged by an ?Low-Side Driver Sink On-Resistance (0.4?) internal diode allows use of N-channel MOSFETs in Prevents dV/dT Related Shoot-Through half-bridge configuration.Current The TPS28226features a 3-state PWM input ?3-State PWM Input for Power Stage Shutdown compatible with all multi-phase controllers employing 3-state output feature.As long as the input stays ?Space Saving Enable (input)and Power Good within 3-state window for the 250-ns hold-off time,the (output)Signals on Same Pin driver switches both outputs low.This shutdown ?Thermal Shutdown mode prevents a load from the reversed-?UVLO Protection output-voltage.?Internal Bootstrap Diode The other features include under voltage lockout,?Economical SOIC-8and Thermally Enhanced thermal shutdown and two-way enable/power good 3-mm x 3-mm DFN-8Packages signal.Systems without 3-state featured controllers can use enable/power good input/output to hold both ?High Performance Replacement for Popular outputs low during shutting down. 3-State Input Drivers The TPS28226is offered in an economical SOIC-8 and thermally enhanced low-size Dual Flat No-Lead (DFN-8)packages.The driver is specified in the ?Multi-Phase DC-to-DC Converters with Analog extended temperature range of –40°C to 125°C with or Digital Control the absolute maximum junction temperature 150°C.? Desktop and Server VRMs and EVRDs ? Portable/Notebook Regulators ?Synchronous Rectification for Isolated Power Supplies Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

同步整流的基本工作原理

同步整流的基本工作原理 https://www.sodocs.net/doc/2d13205990.html,文章出处：发布时间：2008/10/09 | 6869 次阅读| 1次推荐| 0条留言 Samtec连接器完整的信号来源开关，电源限时折扣最低45折每天新产品时刻新体验ARM Cortex-M3内核微控制器最新电子元器件资料免费下载完整的15A开关模式电源首款面向小型化定向照明应用代替 图1（a）所示为N沟道功率MOS管构成的同步整流管SR和SBD整流二极管的电路图形符号，整流二极管有两个极：即阳极A和阴极K。功率MOS管有三个极：即漏极D、源极S和门极G。在用做同步整流管时，将功率MOS管反接使用，即源极S接电源正端，相当于二极管的阳极A；漏极D接电压负端，相当于二极管的阴极K；当功率MOS管在门极G信号的作用下导通时，电流电源极S流向漏极D。而功率MOS管作为开关使用时，漏极D接电源正端，源极S接电压负端；导通时，相当于开关闭合，电流由漏极D流向源极S。 图1 同步整流管和整流二极管 同步整流管SR及整流二极管构成的半波整流电路如图1（b）所示。当SR的门极驱动电压ug，与正弦波电源电压仍同步变化时，则负载R上得到的是与二极管整流电路相同的半波正弦波电压波形1fR。 同步整流管的源一漏极之间有寄生的体二极管，还有输出结电容（未画出），驱动信号加在门极和源极（G-S）之间，是一种可控的开关器件。皿关断时，电流仍然可以由体二极管流通。不过m体二极管的正向导通压降和反向恢复时间都比SBD大得多，因此，一旦电流流过SR的体二极管，则整流损耗将明显增加。

由于同步整流是由可控的三端半导体开关器件来实现的，因此必须要有符合一定时序关系的门极驱动信号去控制它，使其像一个二极管一样地导通和关断。驱动方法对银的整体性能影响很大，因此，门极驱动信号往往是设计同步整流电路时必须要解决的首要问题。例如，SR开通过早或关断过晚，都可能造成短路，而开通过晚或关断过早又可能使SR的体二极管导通，使整流损耗和器件应力增大。 综上所述，当功率MOS管反接时可以作为SR使用，其特点如下： （1）SR是一个可控的三极开关器件，在门极和源极之间加人驱动信号时，可以控制功率MOS管源极S和漏极D之间的通/断。 （2）门极驱动信号和源极电压同步，如源极为高电平时，驱动信号也是高电平则MOS 管导通；反之，源极为低电平时，驱动信号也是低电平，则MOS管关断；这样就自然实现了整流，而且电流也只能由源极s流向漏极D。由于是通过门极信号和源极电压同步来实现整流的，因此把这种整流方式称为同步整流。 （3）用于PWM开关转换器中的同步整流管SD代替SBD作为整流管或续流工作时，必须保证门极有正确的控制时序，使其工作与PWM开关转换器的主开关管同步协调工作。因此不同的开关转换器主电路，其同步整流管的控制时序也是不同的。同步整流开关管的控制时序将在后面进行介绍。 （4）在功率MOS管反接的情况下，其固有的体二极管极性却是正向的。有时要利用它先导通，以便过渡到功率MOS管进入整流状态。但由于体二极管的正向压降较大，常常不希望它导通或导通时问过长。

同步整流电路分析

同步整流电路分析 一、传统二极管整流电路面临的问题 近年来，电子技术的发展，使得电路的工作电压越来越低、电流越来越大。低电压工作有利于降低电路的整体功率消耗，但也给电源设计提出了新的难题。 开关电源的损耗主要由3部分组成：功率开关管的损耗，高频变压器的损耗，输出端整流管的损耗。在低电压、大电流输出的情况下，整流二极管的导通压降较高，输出端整流管的损耗尤为突出。快恢复二极管（FRD）或超快恢复二极管（SRD）可达1.0～1.2V，即使采用低压降的肖特基二极管（SBD），也会产生大约0.6V的压降，这就导致整流损耗增大，电源效率降低。 举例说明，目前笔记本电脑普遍采用3.3V甚至1.8V或1.5V的供电电压，所消耗的电流可达20A。此时超快恢复二极管的整流损耗已接近甚至超过电源输出功率的50％。即使采用肖特基二极管，整流管上的损耗也会达到（18％～40％）P O，占电源总损耗的60％以上。因此，传统的二极管整流电路已无法满足实现低电压、大电流开关电源高效率及小体积的需要，成为制约DC／DC变换器提高效率的瓶颈。 二、同步整流的基本电路结构 同步整流是采用通态电阻极低的专用功率MOSFET，来取代整流二极管以降低整流损耗的一项新技术。它能大大提高DC／DC变换器的效率并且不存在由肖特基势垒电压而造成的死区电压。功率MOSFET属于电压控制型器件，它在导通时的伏安特性呈线性关系。用功率MOSFET做整流器时，要求栅极电压必须与被整流电压的相位保持同步才能完成整流功能，故称之为同步整流。 1、基本的变压器抽头方式双端自激、隔离式降压同步整流电路

2、单端自激、隔离式降压同步整流电路 图1 单端降压式同步整流器的基本原理图 基本原理如图1所示，V1及V2为功率MOSFET，在次级电压的正半周，V1导通，V2关断，V1起整流作用；在次级电压的负半周，V1关断，V2导通，V2起到续流作用。同步整流电路的功率损耗主要包括V1及V2的导通损耗及栅极驱动损耗。当开关频率低于1MHz时，导通损耗占主导地位；开关频率高于1MHz时，以栅极驱动损耗为主。 3、半桥他激、倍流式同步整流电路

同步整流电路的驱动方式综述

同步整流电路的驱动方式综述 预研部余恒23343 一、问题提出： 为了适应电子、通信设备和大规模集成电路的供电要求，DC/DC 模块电源输出电压越来越低，而输出电流却越来越大。传统的肖特基整流方式逐渐被同步整流方式所取代。用低导通电阻MOSFET代替常规肖特基整流/续流二极管，可以大大降低整流部分的功耗，提高变换器的性能，实现电源的高效率，高功率密度。同步整流已经相当流行。但是用MOS代替肖特基二极管势必带来这样一个问题：同步整流MOS管如何驱动？因为二极管不需要驱动，而MOS管是需要驱动的。对于同步整流管的驱动方式，本人收集了部分资料，做了总结，向各位专家学习。 二、驱动方式探讨： 从总的来说同步整流管的驱动方式分为自驱和外驱。 1、外驱：利用原边等驱动信号来控制整流管的开关，优点是可减 小整流管的死区，而且很容易实现时序。不足之处也是显然的，增加了电路的复杂性、成本和可靠性。 *例如，单端正激谐振复位电路，副边续流管可以由原边信号驱动 （如图），也可以整流管由OUT1控制开通，续流管由OUT2控 *又例如图2,这种电路是为了设计原副边的时序。Driverl为正时，Q1导通，副边Qs2处于工作状态。由于Qs12的导通，Qs1 处于关断状态。死区时间Driverl和Driver2为0，则Qs11、Qs21 导通，Q12、Q22的关断，那么Qs1和Qs2均导通，工作在续流状态。当 Driver2为正时，Qs1导通，Qs2关断，Q2延时导通，这样Qs2处于工作状态，Qs1处于关断状态。同样死区时间Qs1 和Qs2同时续流。 可见通过外驱方式实现了原副边时序，使得在死区时间整流管处于工作状态，就不会经过整流管的体二极管续流，从而减小了续流损耗。

智能同步整流控制IC IR1167A B

智能同步整流控制IC-IR1166/7A-B 开关电源技朮中，使系统效率提升最明显的是同步整流技朮，应对不同的电路拓朴有不同模式的同步整流控制方法，但至今为止，多数同步整流控制IC 需要从初级侧取同步信号，这给同步整流设计工作带来一定的烦锁。I R公司购买专利技术新开发的I R1166/7A-B则是一款能从电源变压器二次侧检测信号作智能式同步整流的控制IC，它不仅不需要从初级侧传输信号，而且能适应多种电路拓朴，适应定频PWM及变频PWM，因此它的问世及应用是开关电源技朮的又一大进步。 下面我们来介绍其功能，特色及应用，主要特色有： * 适应反激变换器的DCM，CRM及CCM三种模式工作。适应LLC式半桥。 * 最高500KHz工作频率。 * 总计7A(IR1166为4A)的输出驱动及关断峰值电流（2A源出5A漏入）的能力。 * 栅驱动输出电压在10.7V～14.5V。 * 50ns关断比例延迟。 * Vcc电压从11.3V～20V。 * 直接检测MOSFET的源漏电压。 * 符合低于1W的Standby能量之星的要求。 I R1167系在开关电源二次侧专用于驱动同步整流MOSFET的控制IC，且

能适应DCM，CCM以及多种电路拓朴。可以工作在定频及变频两种模式，也能用于不对称半桥电路的同步整流。是一款优秀的作品，其共有8（PIN）个端子，功能如下： 1PIN VCC IC供电端，内部有欠压锁定及过压关断保护。在V CC电压低于11.3V时关断，高于20V时关闭，为防止噪声干扰，必须加一支足够的旁路电容。要紧靠IC。 2PIN OVT偏置电压调整，OVT端用于调节关断阈值VTH1的偏移量。此端可选择接到GND，或接到Vcc，或令其浮动，共三种输入偏置调整。此特色可以应对不同水平的MOSFET的RDSON。 3PIN MOT最小导通时间，MOT调节端控制最小导通时间的总量，一旦VTH2穿过第一时间，即给出栅驱动信号，令整流MOSFET导通，因为虚假信号及振荡也会触发输入比较器，所以MOT用于消隐比较器保持MOSFET导通，且维持一个最小时间。 MOT调节范围在200ns到3μs之间，用一支电阻从此端接地即可设定。 4PIN EN使能端，此端用于令IC进入休息，将电压拉到2.5V以下。在休息模式，IC消耗电流总量很小，当然开关功能也被禁止，无法做栅驱动。 5PIN VD漏极电压检测端，用于检测同步整流MOSFET的漏极电压，由于此端电压会比较高，必须小心处理，用合适的方法将其接到漏极，此外在此端不可作滤波或作限流，这会影响IC的性能。 6PIN VS源极电压检测端，用于检测同步整流MOSFET的源极电压，此端

PD同步整流芯片ZCC6908HV替代MP6908

DESCRIPTION The ZCC6908HV is a Low-Drop Diode Emulator IC that, combined with an external switch, replaces Schottky diodes in high-efficiency Flyback converters. The chip regulates the forward drop of an external Synchronous Rectifier (SR) MOSFET to about 40mV and switches it off as soon as the voltage becomes negative. ZCC6908HV can generate its own supply voltage for battery charging applications with low output voltage or high side rectification applications. A programmable ringing detection circuitry prevents ZCC6908HV false turn-on during DCM and Quasi-Resonant operations. ZCC6908HV is available in space saving TSOT23-6 packages. FEATURES ●Operates in a wide output voltage range down to 0V ●Self-supplying for operation with low output voltage rectification without an auxiliary winding ● Works with 12V Standard and 5V Logic Level SR MOSFETS ● Compatible with Energy Star, 1W Standby Requirements ● <30ns Fast Turn-off and Turn-on Delay ● <100uA Quiescent Current ● Supports DCM, Quasi-Resonant and CCM Operations ● Supports both High-side and Low-side Rectification ● Power Savings of Up to 1.5W in a Typical Notebook Adapter ● TSOT23-6 Package Available APPLICATIONS ● Industrial Power Systems ●Distributed Power Systems ●Battery Powered Systems ●Flyback Converters TYPICAL APPLICATION

同步整流技术的发展及应用(上)

同步整流技术的发展及应用（上） 从二十世纪末，由于MOSFET技术大幅度进步，引入开关电源技术中的同步整流技术给开关电源效率的提升带来了巨大的收益。效率提升的百分点从3%~8%，比软开关技术带来的效果要好的多。而且没有多少专利技术的限制。目前使用的同步整流有，自驱动方式的同步整流；辅助绕组控制方式的同步整流；控制IC方式的同步整流。近来已经出现了软开关技术的同步整流方式。这种软开关的含义主要指减少或消除MOSFET的开关损耗，即减少体二极管的导通时间并消除体二极管的反响恢复时间造成的损耗。它首先出现在推挽、全桥电路拓扑中，随之又出现在正激电路拓扑中。软开关方式的同步整流，由于其处理的多为大电流，低电压，所以对效率的提升比初级侧软开关处理的高电压小电流更为有效。为了更精确地控制二次侧同步整流，已有几种PWM控制IC将同步整流控制信号设计在IC内部，用外部元件调节同步整流信号的延迟时间，从而能更准确地做到同步整流的软开关控制。 ?此外功率半导体技术的进步使得MOSFET的导通电阻已经达到低于 2mΩ，开关速度小于20ns。栅驱动电荷小于25nq的先进水平。有些MOSFET的体二极管还做成了快恢复的，这使得DC/DC变换器中只要采用 同步整流技术，初级既使不用软开关技术，效果也已经很不错了。 ?同步整流技术已经成为现代开关电源技术的标志。凡是高水平开关电源，必定有同步整流技术。在使用面上早已不再局限于5V、3.3V、2.5V这些低 输出电压领域，现在上至12V，15V，19V至24V以下输出，几乎都在使用同步整流技术。下面介绍和分析各种同步整流技术的优点、缺点及实现方法。 ?一．自驱动同步整流

反激同步整流

一种反激同步整流DC-DC变换器设计 摘 要： 对反激同步整流在低压小电流DC－DC变换器中的应用进行了研究，介绍了主电路工作原理，几种驱动方式及其优缺点，选择出适合于自驱动同步整流的反激电路拓扑，并通过样机试验，验证了该电路的实用性。 引 言：低压大电流DC-DC模块电源一直占模块电源市场需求的一半左右，对其相关技术的研究有着重要的应用价值。模块电源的高效率是各厂家产品的亮点，也是业界追逐的重要目标之一。同步整流可有效减少整流损耗，与适当的电路拓扑结合，可得到低成本的高效率变换器。本文针对36V-75V输入，3.3V/15A 输出的二次电源模块，在分析同步整流技术的基础上，根据同步整流的特点，选择出适合于自驱动同步整流的反激电路拓扑，进行了详细的电路分析和试验。 反激同步整流 基本的反激电路结构如图1。 其工作原理：主MOSFET Q1导通时，进行电能储存，这时可把变压器看成一个电感，原边绕组电流Ip 上升斜率由dIp/dt=Vs/Lp决定，磁芯不饱和，则Ip 线性增加；磁芯内的磁感应强度将从Br增加到工作峰值Bm；Q1关断时，原边电流将降到零，副边整流管开通，感生电流将出现在副边；按功率恒定原则，副边安匝值与原边安匝值相等。 在稳态时，开关导通期间，变压器内磁通增量△Φ应等于反激期间内的磁通变化量，即： △Φ＝VsTon / Np＝Vs'Toff / Ns 从此式可见，如果磁通增量相等的工作点稳定建立时，变压器原边绕组每匝的伏－秒值必然等于副边每匝绕组的伏－秒值。 反激变换器的拓扑实际就是一个BUCK－BOOST组合的变换器拓扑的应用，而且如果副边采用同步整流，电路总是工作于CCM的模式下，其电压增益 M＝Vo/Vs＝K·D/(1－D)(K为原副边匝数比) 用PMOSFET和MOSFET替代图1中的萧特基二极管，可以实现同步整流的4种电路结构如图2和图3 反激电路的开关电压波形见图4，是标准的矩形波，非常适合同步整流驱动。设计的关键点在于同步整流管的位置与驱动电路的结构配合、波形的整形限幅和死区控制。 图1 基本反激电路结构图

智能同步整流控制IC

电子知识 IR1166/7A-B(1)同步整流(50)IC(288) 摘要：IR1166/7A-B则是一款能从电源变压器二次侧检测信号作智能式同步整流的控制IC，它不仅不需要从初级侧传输信号，而且能适应多种电路拓朴，还可应用于定频PWM及变频PWM等方面。文中详细介绍了IR1166/7A-B的主要特点、引脚功能、内部结构及典型应用。 关键词：IR1166/7;开关电源;整流 至今为止，多数同步整流控制IC需要从初级侧取同步信号。IR公司购买专利技术新开发的IR1166/7A-B则是一款能从电源变压器二次侧检测信号作智能式同步整流的控制IC，它不仅不需要从初级侧传输信号，而且能适应多种电路拓朴，适应定频PWM及变频PWM。 1 主要特点 IR1167系在开关电源二次侧专用于驱动同步整流MOSFET的控制IC，且能适应DCM、CCM以及多种电路拓朴。可以工作在定频及变频两种模式，也能用于不对称半桥电路的同步整流，其主要特色有： ◇适应反激变换器的DCM、CRM及CCM三种模式工作，还适用于LLC式半桥。 ◇具有最高500kHz工作频率。 ◇可提供总计7A(IR1166为4A)的输出驱动及关断峰值电流(2A源出5A漏入)的能力。 ◇其栅驱动输出电压在10.7～14.5V。 ◇可提供50ns关断比例延迟。 ◇VCC电压从11.3～20V。

◇可直接检测MOSFET的源漏电压。 ◇符合低于1W的Standby能量之星的要求。 2 引脚功能 IR1166/7A-B共有8(PIN)个端子，其主要引脚功能如下： 1PIN VCC IC供电端，内部有欠压锁定及过压关断保护。在VCC电压低于11.3V时关断，高于20V时关闭，为防止噪声干扰，必须在紧靠IC处加一个足够大的旁路电容。 2PIN OVT偏置电压调整，OVT端用于调节关断阈值VTH1的偏移量。此端可选择接到GND，或接到VCC，或令其浮动，共三种输入偏置调整。此特色可以应对不同水平的MOSFET的RDSON。 3PIN MOT最小导通时间，MOT调节端控制最小导通时间的总量，一旦VTH2穿过第一时间，即给出栅驱动信号，令整流MOSFET导通，因为虚假信号及振荡也会触发输入比较器，所以MOT用于消隐比较器保持MOSFET导通，且维持一个最小时间。MOT调节范围在200ns到3μs之间，与地之间接一支电阻即可实现调节。 4PIN EN使能端，此端可使IC进入休息模式，将电压拉到2.5V以下。在休息模式，IC消耗电流总量很小，当然开关功能也被禁止，无法做栅驱动。 5PIN VD漏极电压检测端，用于检测同步整流MOSFET的漏极电压，由于此端电压会比较高，必须小心处理，用合适的方法将其接到漏极，此外在此端不可作滤波或作限流，这会影响IC的性能。 6PIN VS源极电压检测端，用于检测同步整流MOSFET 的源极电压，此端必须直接接于电源的GMD及IC的(7)PIN，要用Kelvin接法，尽可能靠近MOSFET的源极端子。

同步整流技术的发展及应用

同步整流技术的发展及应用 从二十世纪末，由于MOSFET技术大幅度进步，引入开关电源技术中的同步整流技术给开关电源效率的提升带来了巨大的收益。效率提升的百分点从3%~8%，比软开关技术带来的效果要好的多。而且没有多少专利技术的限制。目前使用的同步整流有，自驱动方式的同步整流；辅助绕组控制方式的同步整流；控制IC方式的同步整流。近来已经出现了软开关技术的同步整流方式。这种软开关的含义主要指减少或消除MOSFET的开关损耗，即减少体二极管的导通时间并消除体二极管的反响恢复时间造成的损耗。它首先出现在推挽、全桥电路拓扑中，随之又出现在正激电路拓扑中。软开关方式的同步整流，由于其处理的多为大电流，低电压，所以对效率的提升比初级侧软开关处理的高电压小电流更为有效。为了更精确地控制二次侧同步整流，已有几种PWM控制IC将同步整流控制信号设计在IC内部，用外部元件调节同步整流信号的延迟时间，从而能更准确地做到同步整流的软开关控制。 ?此外功率半导体技术的进步使得MOSFET的导通电阻已经达到低于 2mΩ，开关速度小于20ns。栅驱动电荷小于25nq的先进水平。有些MOSFET的体二极管还做成了快恢复的，这使得DC/DC变换器中只要采用 同步整流技术，初级既使不用软开关技术，效果也已经很不错了。 ?同步整流技术已经成为现代开关电源技术的标志。凡是高水平开关电源，必定有同步整流技术。在使用面上早已不再局限于5V、3.3V、2.5V这些低 输出电压领域，现在上至12V，15V，19V至24V以下输出，几乎都在使用同步整流技术。下面介绍和分析各种同步整流技术的优点、缺点及实现方法。 ?一．自驱动同步整流